Daewoong Lee
Orcid: 0000-0003-0197-1565
According to our database1,
Daewoong Lee
authored at least 11 papers
between 2015 and 2024.
Collaborative distances:
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Bibliography
2024
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ.
IEEE J. Solid State Circuits, 2023
2022
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2015
An integrated time register and arithmetic circuit with combined operation for time-domain signal processing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015