Douglas J. Gorny

According to our database1, Douglas J. Gorny authored at least 2 papers between 1996 and 1997.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1997
Instruction buffering to reduce power in processors for signal processing.
IEEE Trans. Very Large Scale Integr. Syst., 1997

1996
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996


  Loading...