Katsuro Sasaki

According to our database, Katsuro Sasaki authored at least 7 papers between 1994 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

Instruction buffering to reduce power in processors for signal processing.

Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki

IEEE Trans. Very Large Scale Integr. Syst., 1997

1996

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.

Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.

Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome

IEEE J. Solid State Circuits, April, 1995

Half-swing clocking scheme for 75% power saving in clocking circuitry.

Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki

IEEE J. Solid State Circuits, April, 1995

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.

Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

IEEE J. Solid State Circuits, March, 1995

Trends in low-power RAM circuit technologies.

Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome

Proc. IEEE, 1995

1994

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers.

Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki

IEEE J. Solid State Circuits, April, 1994