Raminder Singh Bajwa

According to our database1, Raminder Singh Bajwa authored at least 16 papers between 1993 and 2001.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2001
Architecture-level power estimation and design experiments.
ACM Trans. Design Autom. Electr. Syst., 2001

1998
A unified approach in the analysis of latches and flip-flops for low-power systems.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Comparative analysis of latches and flip-flops for high-performance systems.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Validation of an Architectural Level Power Analysis Technique.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Instruction buffering to reduce power in processors for signal processing.
IEEE Trans. VLSI Syst., 1997

Mixed-autonomy local interconnect for reconfigurable SIMD arrays.
Proceedings of the Fourth International on High-Performance Computing, 1997

1996
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Simultaneous speech segmentation and phoneme recognition using dynamic programming.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995
The MGAP's programming environment and the *C++ language.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Reducing the number of counters needed for integer multiplication.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
IEEE Trans. Computers, 1994

A SIMD solution to the sequence comparison problem on the MGAP.
Proceedings of the International Conference on Application Specific Array Processors, 1994

Rapid prototyping with programmable control paths.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. VLSI Syst., 1993

A Massively Parallel, Micro-Grained VLSI Architecture.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Image Processing with the MGAP: A Cost Effective Solution.
Proceedings of the Seventh International Parallel Processing Symposium, 1993


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