Douglas M. Carmean

According to our database1, Douglas M. Carmean authored at least 14 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2020
A Scalable Decoder Micro-architecture for Fault-Tolerant Quantum Computing.
CoRR, 2020

2019
DNA Data Storage and Hybrid Molecular-Electronic Computing.
Proc. IEEE, 2019

A case for superconducting accelerators.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2017
Toward a DNA-Based Archival Storage System.
IEEE Micro, 2017

Taming the instruction bandwidth of quantum computers via hardware-managed error correction.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study.
Proceedings of the International Symposium on Memory Systems, 2017

Augmenting Interpersonal Communication through Connected Lighting.
Proceedings of the 2017 CHI Conference on Human Factors in Computing Systems, 2017

2016
A DNA-Based Archival Storage System.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2014
Playing with emotions: sentiment design for public space.
Proceedings of the first ACM SIGCHI annual symposium on Computer-human interaction in play, Toronto, ON, Canada, October 19, 2014

2013
Power modeling and thermal management techniques for manycores.
Proceedings of the 2013 IEEE Symposium on Computers and Communications, 2013

Demonstrating PIXEE: pictures, interaction and emotional expression.
Proceedings of the 2013 ACM SIGCHI Conference on Human Factors in Computing Systems, 2013

PIXEE: pictures, interaction and emotional expression.
Proceedings of the 2013 ACM SIGCHI Conference on Human Factors in Computing Systems, 2013

2001
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit.
IEEE J. Solid State Circuits, 2001


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