Moinuddin K. Qureshi

According to our database1, Moinuddin K. Qureshi authored at least 59 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2018
CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement.
CoRR, 2018

A Case for Variability-Aware Policies for NISQ-Era Quantum Computers.
CoRR, 2018

LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency.
CoRR, 2018

ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Top Picks from the 2016 Computer Architecture Conferences.
IEEE Micro, 2017

Taming the instruction bandwidth of quantum computers via hardware-managed error correction.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study.
Proceedings of the International Symposium on Memory Systems, 2017

BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM.
Proceedings of the International Symposium on Memory Systems, 2017

DICE: Compressing DRAM Caches for Bandwidth and Capacity.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

FlashBlox: Achieving Both Performance Isolation and Uniform Lifetime for Virtualized SSDs.
Proceedings of the 15th USENIX Conference on File and Storage Technologies, 2017

FlashGuard: Leveraging Intrinsic Flash Properties to Defend Against Encryption Ransomware.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

2016
Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures.
TACO, 2016

FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems.
TACO, 2016

An Evolutionary Study of Linux Memory Management for Fun and Profit.
Proceedings of the 2016 USENIX Annual Technical Conference, 2016

CANDY: Enabling coherent DRAM caches for multi-node systems.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

XED: Exposing On-Die Error Detection Information for Strong Memory Reliability.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Architectural Support for Mitigating Row Hammering in DRAM Memories.
Computer Architecture Letters, 2015

Unified address translation for memory-mapped SSDs with FlashMap.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Reducing read latency of phase change memory via early read and Turbo Read.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems.
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

Reducing Refresh Power in Mobile Devices with Morphable ECC.
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

DEUCE: Write-Efficient Encryption for Non-Volatile Memories.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Refresh pausing in DRAM memory systems.
TACO, 2014

NVRAM-aware Logging in Transaction Systems.
PVLDB, 2014

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Balancing context switch penalty and response time with elastic time slicing.
Proceedings of the 21st International Conference on High Performance Computing, 2014

2013
Embedded tutorial - Emerging memory technologies: What it means for computer system designers.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A case for Refresh Pausing in DRAM memory systems.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Operating SECDED-based caches at ultra-low voltage with FLAIR.
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

2012
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

PreSET: Improving performance of phase change memories by exploiting asymmetry in write times.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011
Phase Change Memory: From Devices to Systems
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2011

Pay-As-You-Go: low-overhead hard-error correction for phase change memories.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Practical and secure PCM systems by online detection of malicious write streams.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Accelerating Critical Section Execution with Asymmetric Multicore Architectures.
IEEE Micro, 2010

Morphable memory system: a robust architecture for exploiting multi-level phase change memories.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Feedback-directed pipeline parallelism.
Proceedings of the 19th International Conference on Parallel Architecture and Compilation Techniques, 2010

2009
A tagless coherence directory.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Scalable high performance main memory system using phase-change memory technology.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Adaptive Spill-Receive for robust high-performance caching in CMPs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Accelerating critical section execution with asymmetric multi-core architectures.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching.
IEEE Micro, 2008

Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

Adaptive insertion policies for managing shared caches.
Proceedings of the 17th International Conference on Parallel Architecture and Compilation Techniques, 2008

2007
Adaptive insertion policies for high performance caching.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

A Case for MLP-Aware Cache Replacement.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005
The V-Way Cache: Demand Based Associativity via Global Replacement.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005


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