Moinuddin K. Qureshi

Bolin Wang

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021

Quantum Computing and the Design of the Ultimate Accelerator.

[BibT_eX]

[DOI]

IEEE Micro, 2021

Gradient Inversion Attack: Leaking Private Labels in Two-Party Split Learning.

[BibT_eX]

[DOI]

CoRR, 2021

Enabling Inference Privacy with Adaptive Noise Injection.

[BibT_eX]

[DOI]

Ousmane Dia

CoRR, 2021

SmaQ: Smart Quantization for DNN Training by Exploiting Value Clustering.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

A Day In the Life of a Quantum Error.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design.

[BibT_eX]

[DOI]

Proceedings of the 30th USENIX Security Symposium, 2021

Bespoke Cache Enclaves: Fine-Grained and Scalable Isolation from Cache Side-Channels via Flexible Set-Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

JigSaw: Boosting Fidelity of NISQ Programs via Measurement Subsetting.

[BibT_eX]

[DOI]

Poulami Das

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

ADAPT: Mitigating Idling Errors in Qubits via Adaptive Dynamical Decoupling.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Protecting DNNs from Theft using an Ensemble of Diverse Models.

[BibT_eX]

[DOI]

Atul Prakash

Proceedings of the 9th International Conference on Learning Representations, 2021

MAZE: Data-Free Model Stealing Attack Using Zeroth-Order Gradient Estimation.

[BibT_eX]

[DOI]

Atul Prakash

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion.

[BibT_eX]

[DOI]

Christopher W. Fletcher

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020

A Scalable Decoder Micro-architecture for Fault-Tolerant Quantum Computing.

[BibT_eX]

[DOI]

Poulami Das

Christopher A. Pattison

CoRR, 2020

Defending Against Model Stealing Attacks With Adaptive Misinformation.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019

With New Memories Come New Challenges.

[BibT_eX]

[DOI]

IEEE Micro, 2019

Lookout for Zombies: Mitigating Flush+Reload Attack on Shared Caches by Monitoring Invalidated Lines.

[BibT_eX]

[DOI]

CoRR, 2019

Improving Adversarial Robustness of Ensembles with Diversity Training.

[BibT_eX]

[DOI]

CoRR, 2019

Mitigating Measurement Errors in Quantum Computers by Exploiting State-Dependent Bias.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

CleanupSpec: An "Undo" Approach to Safe Speculation.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A Case for Multi-Programming Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

New attacks and defense for encrypted-address cache.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems.

[BibT_eX]

[DOI]

Zeshan A. Chishti

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Enabling Transparent Memory-Compression for Commodity Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM.

[BibT_eX]

[DOI]

Bahar Asgari

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

A case for superconducting accelerators.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement.

[BibT_eX]

[DOI]

CoRR, 2018

A Case for Variability-Aware Policies for NISQ-Era Quantum Computers.

[BibT_eX]

[DOI]

CoRR, 2018

LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency.

[BibT_eX]

[DOI]

CoRR, 2018

Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

Top Picks from the 2016 Computer Architecture Conferences.

[BibT_eX]

[DOI]

IEEE Micro, 2017

Taming the instruction bandwidth of quantum computers via hardware-managed error correction.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study.

[BibT_eX]

[DOI]

Douglas M. Carmean

Proceedings of the International Symposium on Memory Systems, 2017

BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

DICE: Compressing DRAM Caches for Bandwidth and Capacity.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

FlashBlox: Achieving Both Performance Isolation and Uniform Lifetime for Virtualized SSDs.

[BibT_eX]

[DOI]

Proceedings of the 15th USENIX Conference on File and Storage Technologies, 2017

FlashGuard: Leveraging Intrinsic Flash Properties to Defend Against Encryption Ransomware.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

2016

Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures.

[BibT_eX]

[DOI]

David A. Roberts

ACM Trans. Archit. Code Optim., 2016

FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems.

[BibT_eX]

[DOI]

David A. Roberts

ACM Trans. Archit. Code Optim., 2016

Energy Aware Persistence: Reducing the Energy Overheads of Persistent Memory.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2016

An Evolutionary Study of Linux Memory Management for Fun and Profit.

[BibT_eX]

[DOI]

Jian Huang

Karsten Schwan

Proceedings of the 2016 USENIX Annual Technical Conference, 2016

CANDY: Enabling coherent DRAM caches for multi-node systems.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

XED: Exposing On-Die Error Detection Information for Strong Memory Reliability.

[BibT_eX]

[DOI]

Vilas Sridharan

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015

Architectural Support for Mitigating Row Hammering in DRAM Memories.

[BibT_eX]

[DOI]

Dae-Hyun Kim

IEEE Comput. Archit. Lett., 2015

Unified address translation for memory-mapped SSDs with FlashMap.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Reducing read latency of phase change memory via early read and Turbo Read.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

Reducing Refresh Power in Mobile Devices with Morphable ECC.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

DEUCE: Write-Efficient Encryption for Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Refresh pausing in DRAM memory systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

NVRAM-aware Logging in Transaction Systems.

[BibT_eX]

[DOI]

Jian Huang

Karsten Schwan

Proc. VLDB Endow., 2014

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures.

[BibT_eX]

[DOI]

David A. Roberts

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache.

[BibT_eX]

[DOI]

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Balancing context switch penalty and response time with elastic time slicing.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on High Performance Computing, 2014

2013

Embedded tutorial - Emerging memory technologies: What it means for computer system designers.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates.

[BibT_eX]

[DOI]

Dae-Hyun Kim

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A case for Refresh Pausing in DRAM memory systems.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Operating SECDED-based caches at ultra-low voltage with FLAIR.

[BibT_eX]

[DOI]

Zeshan Chishti

Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

2012

Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design.

[BibT_eX]

[DOI]

Gabriel H. Loh

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

PreSET: Improving performance of phase change memories by exploiting asymmetry in write times.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011

Phase Change Memory: From Devices to Systems

[BibT_eX]

[DOI]

Sudhanva Gurumurthi

Bipin Rajendran

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01735-3, 2011

Pay-As-You-Go: low-overhead hard-error correction for phase change memories.

[BibT_eX]

[DOI]

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Practical and secure PCM systems by online detection of malicious write streams.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010

Accelerating Critical Section Execution with Asymmetric Multicore Architectures.

[BibT_eX]

[DOI]

IEEE Micro, 2010

Morphable memory system: a robust architecture for exploiting multi-level phase change memories.

[BibT_eX]

[DOI]

Luis Alfonso Lastras-Montaño

Michele Franceschini

John P. Karidis

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing.

[BibT_eX]

[DOI]

Luis Alfonso Lastras-Montaño

Michele Franceschini

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Feedback-directed pipeline parallelism.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

A tagless coherence directory.

[BibT_eX]

[DOI]

Jason Zebchuk

Vijayalakshmi Srinivasan

Andreas Moshovos

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling.

[BibT_eX]

[DOI]

John P. Karidis

Michele Franceschini

Vijayalakshmi Srinivasan

Luis A. Lastras

Bülent Abali

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Scalable high performance main memory system using phase-change memory technology.

[BibT_eX]

[DOI]

Vijayalakshmi Srinivasan

Jude A. Rivers

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Adaptive Spill-Receive for robust high-performance caching in CMPs.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Accelerating critical section execution with asymmetric multi-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008

Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching.

[BibT_eX]

[DOI]

IEEE Micro, 2008

Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs.

[BibT_eX]

[DOI]

M. Aater Suleman

Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

Adaptive insertion policies for managing shared caches.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

Adaptive insertion policies for high performance caching.

[BibT_eX]

[DOI]

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines.

[BibT_eX]

[DOI]

M. Aater Suleman

Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

A Case for MLP-Aware Cache Replacement.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

2005

The V-Way Cache: Demand Based Associativity via Global Replacement.

[BibT_eX]

[DOI]

David Thompson

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors.

[BibT_eX]

[DOI]

Onur Mutlu