Prashant J. Nair

Kevin J. Barker

Ang Li

CoRR, 2023

Ad-Rec: Advanced Feature Interactions to Address Covariate-Shifts in Recommendation Networks.

[BibT_eX]

[DOI]

CoRR, 2023

Enabling Scalable VQE Simulation on Leading HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Structural Coding: A Low-Cost Scheme to Protect CNNs from Large-Granularity Memory Faults.

[BibT_eX]

[DOI]

Ali Asgari Khoshouyeh

Proceedings of the International Conference for High Performance Computing, 2023

FLuID: Mitigating Stragglers in Federated Learning using Invariant Dropout.

[BibT_eX]

[DOI]

Irene Wang

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems.

[BibT_eX]

[DOI]

Jeonghyun Woo

Gururaj Saileshwar

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

HuffDuff: Stealing Pruned DNNs from Sparse Accelerators.

[BibT_eX]

[DOI]

Dingqing Yang

Mieszko Lis

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022

The Dirty Secret of SSDs: Embodied Carbon.

[BibT_eX]

[DOI]

Swamit S. Tannu

CoRR, 2022

Heterogeneous Acceleration Pipeline for Recommendation System Training.

[BibT_eX]

[DOI]

CoRR, 2022

TQSim: A Case for Reuse-Focused Tree-Based Quantum Circuit Simulation.

[BibT_eX]

[DOI]

CoRR, 2022

AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021

Accelerating Recommendation System Training by Leveraging Popular Choices.

[BibT_eX]

[DOI]

Proc. VLDB Endow., 2021

High-Performance Training by Exploiting Hot-Embeddings in Recommendation Systems.

[BibT_eX]

[DOI]

CoRR, 2021

A Case for Emerging Memories in DNN Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches.

[BibT_eX]

[DOI]

Beomjun Kim

Seokin Hong

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2DCC: Cache Compression in Two Dimensions.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Thesaurus: Efficient Cache Compression via Dynamic Clustering.

[BibT_eX]

[DOI]

Amin Ghasemazar

Mieszko Lis

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A Case for Multi-Programming Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM.

[BibT_eX]

[DOI]

Bahar Asgari

Prashant Jayaprakash Nair

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

2018

LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency.

[BibT_eX]

[DOI]

CoRR, 2018

Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.

[BibT_eX]

[DOI]

Seokin Hong

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

Architectural Techniques to Enable Reliable and Scalable Memory Systems.

[BibT_eX]

[DOI]

CoRR, 2017

Taming the instruction bandwidth of quantum computers via hardware-managed error correction.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

DICE: Compressing DRAM Caches for Bandwidth and Capacity.

[BibT_eX]

[DOI]

Vinson Young

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016

Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures.

[BibT_eX]

[DOI]

David A. Roberts

ACM Trans. Archit. Code Optim., 2016

FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems.

[BibT_eX]

[DOI]

David A. Roberts

ACM Trans. Archit. Code Optim., 2016

XED: Exposing On-Die Error Detection Information for Strong Memory Reliability.

[BibT_eX]

[DOI]

Vilas Sridharan

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

Architectural Support for Mitigating Row Hammering in DRAM Memories.

[BibT_eX]

[DOI]

Dae-Hyun Kim

IEEE Comput. Archit. Lett., 2015

Reducing read latency of phase change memory via early read and Turbo Read.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

Reducing Refresh Power in Mobile Devices with Morphable ECC.

[BibT_eX]

[DOI]

Chia-Chen Chou

Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

DEUCE: Write-Efficient Encryption for Non-Volatile Memories.

[BibT_eX]

[DOI]

Vinson Young

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Refresh pausing in DRAM memory systems.

[BibT_eX]

[DOI]

Chia-Chen Chou

ACM Trans. Archit. Code Optim., 2014

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures.

[BibT_eX]

[DOI]

David A. Roberts

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates.

[BibT_eX]

[DOI]

Dae-Hyun Kim

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A case for Refresh Pausing in DRAM memory systems.

[BibT_eX]

[DOI]

Chia-Chen Chou