E. Ray Hsieh

According to our database, E. Ray Hsieh authored at least 7 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks.

Yi Xiang Huang, Y. S. Lin, P. S. Huang, E. Ray Hsieh

IEEE Solid State Circuits Lett., 2026

2025

µPUA-Net: PowerMLP Model Size Shrinking Method with Accuracy Maintaining.

Yu-Shan Chou, You-Jin Liu, Kai-Lun Pien, Tong-Hou Cheong, Chieh-Chen Yu, Ying-Hui Cheng, Yu-Hsuan Chiang, E. Ray Hsieh, Chien-Chang Chen

Proceedings of the Segmentation, Classification, and Synthesis for Brain Tumors and Traumatic Brain Injuries, 2025

2023

3-bits-per-cell 2T32CFE nvTCAM by Angstrom-laminated Ferroelectric Layers with 10¹¹ Cycles of Endurance and 4.92V of Ultra-wide Memory-windows for In-memory-searching.

E. Ray Hsieh, Ying-Tsan Tang, Cheng-Rui Liu, Sheng-Min Wang, Y. L. Hsueh, R. Q. Lin, Yi Xiang Huang, Yu-Ting Chen

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFE to Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰ Cycles of Endurance, and Decade Lifetime at 103 °C.

E. Ray Hsieh, J. K. Chang, T. Y. Tang, Y. J. Li, C. W. Liang, M. Y. Lin, S. Y. Huang, C. J. Su, J. C. Guo, Steve S. Chung

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path.

W. Y. Yang, E. Ray Hsieh, C. H. Cheng, B. Y. Chen, K. S. Li, Steve S. Chung

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory.

E. Ray Hsieh, H. W. Cheng, Z. H. Huang, C. H. Chuang, S. P. Yang, Steve S. Chung

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019

The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond.

E. Ray Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019