Eduardo Ortega
Orcid: 0000-0002-1671-6279
According to our database1,
Eduardo Ortega
authored at least 10 papers
between 2023 and 2025.
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Bibliography
2025
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025
Discretized-Isolation Forest: Memory- and Compute-Efficient Unsupervised Anomaly Detection for Resource-Constrained Internet of Things Edge Devices.
IEEE Internet Things J., January, 2025
Runtime Security Analysis of Monolithic 3D Embedded DRAM with Oxide-Channel Transistor.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse Engineering.
IEEE Trans. Very Large Scale Integr. Syst., August, 2024
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
Enhancing efficiency in spaceborne phased array systems: MVDR algorithm and FPGA integration.
Digit. Signal Process., 2024
Proceedings of the IEEE International Test Conference, 2024
2023
Axioms, December, 2023
Proceedings of the IEEE International Test Conference, 2023