Biresh Kumar Joardar

Orcid: 0000-0002-7668-2824

According to our database1, Biresh Kumar Joardar authored at least 50 papers between 2017 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Building Reliable Arithmetic Multipliers Under NBTI Aging and Process Variations.
CoRR, May, 2026

Attacking AI Accelerators by Leveraging Arithmetic Properties of Addition.
CoRR, March, 2026

Security Vulnerabilities of Semiconductor Memories.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

2025
HePGA: A Heterogeneous Processing-in-Memory based GNN Training Accelerator.
CoRR, August, 2025

Localization of Data Compromised by Hardware Attacks in Machine Learning Enabled Cyber-Physical Edge Devices.
ACM Trans. Cyber Phys. Syst., July, 2025

GINA: Exploiting Graph Neural Network Layer Features for Energy Efficient Inferencing in NVM-based PIM Accelerators.
ACM Trans. Embed. Comput. Syst., 2025

Aging Attack on Systolic Array-Based AI Accelerators via NBTI-Induced Aging.
Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

DEAR: Dependable 3D Architecture for Robust DNN Training.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

Acceleration of Large Language Models with Emerging Compute and Communication Technology.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2025

2024
HuNT: Exploiting Heterogeneous PIM Devices to Design a 3-D Manycore Architecture for DNN Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

HALO: Communication-Aware Heterogeneous 2.5-D System for Energy-Efficient LLM Execution at Edge.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators.
ACM Trans. Design Autom. Electr. Syst., 2024

Introduction to the Special Issue on Embedded System Software/Tools.
ACM Trans. Design Autom. Electr. Syst., 2024

SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory<sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2024

Heterogeneous Manycore In-Memory Computing Architectures.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

FARe: Fault-Aware GNN Training on ReRAM-Based PIM Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Machine Learning-Based Rowhammer Mitigation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

ReaLPrune: ReRAM Crossbar-Aware Lottery Ticket Pruning for CNNs.
IEEE Trans. Emerg. Top. Comput., 2023

Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Simply-Track-and-Refresh: Efficient and Scalable Rowhammer Mitigation.
Proceedings of the IEEE International Test Conference, 2023

Energy-Efficient ReRAM-Based ML Training via Mixed Pruning and Reconfigurable ADC.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Attacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write Errors.
Proceedings of the IEEE European Test Symposium, 2023

Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Attacking ReRAM-based Architectures using Repeated Writes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

NoC-enabled 3D Heterogeneous Manycore Systems for Big-Data Applications.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Fault-Tolerant Deep Learning Using Regularization.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Learning to Mitigate Rowhammer Attacks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2021

HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration.
ACM Trans. Design Autom. Electr. Syst., 2021

Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators.
ACM Trans. Embed. Comput. Syst., 2021

AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

ReaLPrune: ReRAM Crossbar-aware Lottery Ticket Pruned CNNs.
CoRR, 2021

Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs: (ICCAD Special Session Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

3D++: Unlocking the Next Generation of High-Performance and Energy-Efficient Architectures using M3D Integration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
MOOS: A Multi-Objective Design Space Exploration and Optimization Framework for NoC Enabled Manycore Systems.
ACM Trans. Embed. Comput. Syst., 2019

Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems.
IEEE Trans. Computers, 2019

NoC-enabled software/hardware co-design framework for accelerating <i>k-mer</i> counting.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design and Optimization of Heterogeneous Manycore Systems Enabled by Emerging Interconnect Technologies: Promises and Challenges.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Taming extreme heterogeneity via machine learning based design of autonomous manycore systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018
Hybrid on-chip communication architectures for heterogeneous manycore systems.
Proceedings of the International Conference on Computer-Aided Design, 2018

High performance collective communication-aware 3D Network-on-Chip architectures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017


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