Arjun Chaudhuri

Orcid: 0000-0001-9353-6397

According to our database1, Arjun Chaudhuri authored at least 44 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., March, 2023

ChipNeMo: Domain-Adapted LLMs for Chip Design.
CoRR, 2023

Innovation Practices Track: Testability and Dependability of AI Hardware and Autonomous Systems.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs <sup>*</sup>.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Functional Test Generation for AI Accelerators using Bayesian Optimization<sup>∗</sup>.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Analysis and Characterization of Defects in FeFETs.
Proceedings of the IEEE International Test Conference, 2023

Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs.
Proceedings of the IEEE International Test Conference, 2023

Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning<sup>*</sup>.
Proceedings of the IEEE European Test Symposium, 2023

Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Fault Modeling, Design-for-Test, and Fault Tolerance for Machine Learning Hardware.
PhD thesis, 2022

Functional Criticality Analysis of Structural Faults in AI Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

C-Testing and Efficient Fault Localization for AI Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Design Automation and Test Solutions for Monolithic 3D ICs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Special Session: Fault Criticality Assessment in AI Accelerators.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Automatic Structural Test Generation for Analog Circuits using Neural Twins.
Proceedings of the IEEE International Test Conference, 2022

Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration.
Proceedings of the IEEE International Test Conference, 2022

Probabilistic Fault Grading for AI Accelerators using Neural Twins.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Structural Test Generation for AI Accelerators using Neural Twins.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Machine Learning for Testing Machine-Learning Hardware: A Virtuous Cycle.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TaintLock: Preventing IP Theft through Lightweight Dynamic Scan Encryption using Taint Bits<sup>*</sup>.
Proceedings of the IEEE European Test Symposium, 2022

Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin<sup>∗</sup>.
Proceedings of the IEEE International Test Conference, 2021

Testing and Fault-Localization Solutions for Monolithic 3D ICs<sup>*</sup>.
Proceedings of the IEEE International Test Conference in Asia, 2021

ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Advances in Design and Test of Monolithic 3-D ICs.
IEEE Des. Test, 2020

Functional Criticality Classification of Structural Faults in AI Accelerators.
Proceedings of the IEEE International Test Conference, 2020

RTL-to-GDS Design Tools for Monolithic 3D ICs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

C-Testing of AI Accelerators <sup>*</sup>.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs<sup>∗</sup>.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Compact Scalable Dynamic TSV IR Drop Compensation for Power Delivery in 3D Packages.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Hardware Fault Tolerance for Binary RRAM Crossbars.
Proceedings of the IEEE International Test Conference, 2019

Fault-Tolerant Neuromorphic Computing Systems.
Proceedings of the IEEE International Test Conference, 2019

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.
Proceedings of the 24th IEEE European Test Symposium, 2019

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors.
Proceedings of the IEEE International Test Conference, 2018

2017
Single chip self-tunable N-input N-output PID control system with integrated analog front-end for miniature robotics.
Proceedings of the 14th IEEE International Conference on Networking, Sensing and Control, 2017

2016
Selective De-noising of Sparse-Coloured Images.
CoRR, 2016

Single Chip Self-Tunable N-Input N-Output PID Control System with Integrated Analog Front-end for Miniature Robotics.
CoRR, 2016


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