Ehsan Aerabi

Orcid: 0000-0002-4433-9466

According to our database1, Ehsan Aerabi authored at least 12 papers between 2015 and 2022.

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Bibliography

2022
CyEnSe: Cyclic energy-aware scheduling for energy-harvested embedded systems.
Microprocess. Microsystems, March, 2022

2021
CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes.
Cryptogr., 2021

2020
Design Space Exploration for Ultra-Low-Energy and Secure IoT MCUs.
ACM Trans. Embed. Comput. Syst., 2020

On a Side Channel and Fault Attack Concurrent Countermeasure Methodology for MCU-based Byte-sliced Cipher Implementations.
IACR Cryptol. ePrint Arch., 2020

You can detect but you cannot hide: Fault Assisted Side Channel Analysis on Protected Software-based Block Ciphers.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

2018
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017
Side channel parameter characteristics of code injection attacks.
ISC Int. J. Inf. Secur., 2017

2016
Hardware enlightening: No where to hide your Hardware Trojans!
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

High output hamming-distance achievement by a greedy logic masking approach.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
The Conjoined Microprocessor.
IACR Cryptol. ePrint Arch., 2015


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