Athanasios Papadimitriou
Orcid: 0000-0002-4127-7554
According to our database1,
Athanasios Papadimitriou
authored at least 29 papers
between 2014 and 2023.
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Bibliography
2023
On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2022
Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained Networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes.
Cryptogr., 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
ACM Trans. Embed. Comput. Syst., 2020
On a Side Channel and Fault Attack Concurrent Countermeasure Methodology for MCU-based Byte-sliced Cipher Implementations.
IACR Cryptol. ePrint Arch., 2020
On a Security-oriented Design Framework for Medical IoT Devices: The Hardware Security Perspective.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
You can detect but you cannot hide: Fault Assisted Side Channel Analysis on Protected Software-based Block Ciphers.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor.
Microprocess. Microsystems, 2019
On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
2018
IEEE Embed. Syst. Lett., 2018
Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2016
Can Algorithm Diversity in Stream Cipher Implementation Thwart (Natural and) Malicious Faults?
IEEE Trans. Emerg. Top. Comput., 2016
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.
Microprocess. Microsystems, 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014