David Hély

According to our database1, David Hély authored at least 60 papers between 2004 and 2018.

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Bibliography

2018
ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods.
J. Hardware and Systems Security, 2018

Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing.
J. Electronic Testing, 2018

Stack Redundancy to Thwart Return Oriented Programming in Embedded Systems.
Embedded Systems Letters, 2018

Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Authentication of Microcontroller Board Using Non-Invasive EM Emission Technique.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Towards an Inherently Secure Run-Time Environment for Medical Devices.
Proceedings of the 2018 IEEE International Congress on Internet of Things, 2018

2017
Secure and Flexible Trace-Based Debugging of Systems-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2017

Key Reconciliation Protocols for Error Correction of Silicon PUF Responses.
IEEE Trans. Information Forensics and Security, 2017

A red team blue team approach towards a secure processor design with hardware shadow stack.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Centrality Indicators for Efficient and Scalable Logic Masking.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A comprehensive hardware/software infrastructure for IP cores design protection.
Proceedings of the International Conference on Field Programmable Technology, 2017

IoT Components LifeCycle Based Security Analysis.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Enhanced Elliptic Curve Scalar Multiplication Secure Against Side Channel Attacks and Safe Errors.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

2016
ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes.
ACM Trans. Design Autom. Electr. Syst., 2016

Can Algorithm Diversity in Stream Cipher Implementation Thwart (Natural and) Malicious Faults?
IEEE Trans. Emerging Topics Comput., 2016

Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

From secured logic to IP protection.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Clock generator behavioral modeling for supply voltage glitch attack effects analysis.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Key Reconciliation Protocols for Error Correction of Silicon PUF Responses.
IACR Cryptology ePrint Archive, 2016

On fault injections for early security evaluation vs. laser-based attacks.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Reusing logic masking to facilitate path-delay-based hardware Trojan detection.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

How logic masking can improve path delay analysis for Hardware Trojan detection.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

High output hamming-distance achievement by a greedy logic masking approach.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Implementation of a secured digital ultralight 14443-type A RFID tag with an FPGA platform.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

On the development of a new countermeasure based on a laser attack RTL fault model.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Secure design-for-debug for Systems-on-Chip.
Proceedings of the 2015 IEEE International Test Conference, 2015

Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A secure design-for-test infrastructure for lifetime security of SoCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Facilitating side channel analysis by obfuscation for Hardware Trojan detection.
Proceedings of the 10th International Design & Test Symposium, 2015

Validation of RTL laser fault injection model with respect to layout information.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014


Fault tolerance evaluation of RFID tags.
Proceedings of the 15th Latin American Test Workshop, 2014

On error models for RTL security evaluations.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Voltage Glitch Attacks on Mixed-Signal Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Emulation based fault injection on UHF RFID transponder.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Experiences in side channel and testing based Hardware Trojan detection.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Assertion based on-line fault detection applied on UHF RFID tag.
Proceedings of the 8th International Design and Test Symposium, 2013

An UHF RFID emulation platform with fault injection and real time monitoring capabilities.
Proceedings of the 8th International Design and Test Symposium, 2013

Run-time detection of hardware Trojans: The processor protection unit.
Proceedings of the 18th IEEE European Test Symposium, 2013

EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2012
A physical unclonable function based on setup time violation.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Malicious key emission via hardware Trojan against encryption system.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Evaluation of a new RFID system performance monitoring approach.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate.
J. Electronic Testing, 2011

SystemC modeling of RFID systems for robustness analysis.
Proceedings of the 19th International Conference on Software, 2011

Read rate profile monitoring for defect detection in RFID Systems.
Proceedings of the 2011 IEEE International Conference on RFID-Technologies and Applications, 2011

Towards middleware-based fault-tolerance in RFID systems.
Proceedings of the 13th European Workshop on Dependable Computing, 2011

Towards an unified IP verification and robustness analysis platform.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2007
Securing Scan Control in Crypto Chips.
J. Electronic Testing, 2007

2006
Secure Scan Techniques: A Comparison.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A secure scan design methodology.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Test control for secure scan designs.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

2004
Scan Design and Secure Chip.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004


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