David Hély
Orcid: 0000-0003-3249-7667
According to our database1,
David Hély
authored at least 105 papers
between 2004 and 2023.
Collaborative distances:
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Bibliography
2023
On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
Microprocess. Microsystems, March, 2022
J. Ambient Intell. Smart Environ., 2022
Hardware Support for Efficient and Low-Power Data Sorting in Massive Data Application: The 3-D Sorting Method.
IEEE Consumer Electron. Mag., 2022
Helper Data Masking for Physically Unclonable Function-Based Key Generation Algorithms.
IEEE Access, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
An Efficient Approach to Model Strong PUF with Multi-Layer Perceptron using Transfer Learning.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine Learning.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2022
Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022
2021
Sensors, 2021
IEEE Embed. Syst. Lett., 2021
CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes.
Cryptogr., 2021
Proceedings of the 17th International Conference on Intelligent Environments, 2021
Efficient Scheduling of Dependent Tasks in Many-Core Real-Time System Using a Hardware Scheduler.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the 2021 IEEE International Conference on Omni-Layer Intelligent Systems, 2021
2020
TrustFlow-X: A Practical Framework for Fine-grained Control-flow Integrity in Critical Systems.
ACM Trans. Embed. Comput. Syst., 2020
ACM Trans. Embed. Comput. Syst., 2020
SN Comput. Sci., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
On a Side Channel and Fault Attack Concurrent Countermeasure Methodology for MCU-based Byte-sliced Cipher Implementations.
IACR Cryptol. ePrint Arch., 2020
Proceedings of the Intelligent Computing, 2020
3D-Sorter: 3D Design of a Resource-Aware Hardware Sorter for Edge Computing Platforms Under Area and Energy Consumption Constraints.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Hardware Security Vulnerability Assessment to Identify the Potential Risks in A Critical Embedded Application.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community.
Proceedings of the IEEE European Test Symposium, 2020
You can detect but you cannot hide: Fault Assisted Side Channel Analysis on Protected Software-based Block Ciphers.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
J. Hardw. Syst. Secur., 2019
Implementation of Password Management System Using Ternary Addressable PUF Generator.
Proceedings of the 16th Annual IEEE International Conference on Sensing, 2019
Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
SHCoT: Secure (and Verified) Hybrid Chain of Trust to Protect from Malicious Software in LightWeight Devices.
Proceedings of the IEEE International Symposium on Software Reliability Engineering Workshops, 2019
Toubkal: A Flexible and Efficient Hardware Isolation Module for Secure Lightweight Devices.
Proceedings of the 15th European Dependable Computing Conference, 2019
2018
ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods.
J. Hardw. Syst. Secur., 2018
J. Electron. Test., 2018
IEEE Embed. Syst. Lett., 2018
Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 2018 IEEE International Congress on Internet of Things, 2018
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
2017
ACM Trans. Design Autom. Electr. Syst., 2017
IEEE Trans. Inf. Forensics Secur., 2017
A red team blue team approach towards a secure processor design with hardware shadow stack.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
Enhanced Elliptic Curve Scalar Multiplication Secure Against Side Channel Attacks and Safe Errors.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017
2016
ACM Trans. Design Autom. Electr. Syst., 2016
Can Algorithm Diversity in Stream Cipher Implementation Thwart (Natural and) Malicious Faults?
IEEE Trans. Emerg. Top. Comput., 2016
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.
Microprocess. Microsystems, 2016
Clock generator behavioral modeling for supply voltage glitch attack effects analysis.
Microprocess. Microsystems, 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Implementation of a secured digital ultralight 14443-type A RFID tag with an FPGA platform.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 10th International Design & Test Symposium, 2015
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
An UHF RFID emulation platform with fault injection and real time monitoring capabilities.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
J. Electron. Test., 2011
Proceedings of the 19th International Conference on Software, 2011
Proceedings of the 2011 IEEE International Conference on RFID-Technologies and Applications, 2011
Proceedings of the 13th European Workshop on Dependable Computing, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2007
2006
Scan Pattern Watermarking.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the 10th European Test Symposium, 2005
2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004