Tohru Moto-Oka

According to our database, Tohru Moto-Oka authored at least 23 papers between 1960 and 1986.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

1986

Interconnection networks for bucket distribution on relational algebra machine GRACE.

Shuichi Sakai, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka

Syst. Comput. Jpn., 1986

Design of secondary storage system of database machine grace using generalized KD-tree.

Shinya Fushimi, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka

Syst. Comput. Jpn., 1986

Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog.

Masahiro Fujita, Shinji Kono, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the Third International Conference on Logic Programming, 1986

1985

Interconnection network for bucket collection on relational algebra machine GRACE.

Shuichi Sakai, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka

Syst. Comput. Jpn., 1985

Algorithm and Performance Evaluation of Adaptive Multidimensional Clustering Technique.

Shinya Fushimi, Masaru Kitsuregawa, Masaya Nakayama, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the 1985 ACM SIGMOD International Conference on Management of Data, 1985

A Note on the Elementary Execution Unit in a Parallel Inference Machine.

Tsutomu Maruyama, Keiji Hirata, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the Logic Programming '85, 1985

Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis.

Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the Logic Programming '85, 1985

Temporal Logic Programming Language Tokio - Programming in Tokio.

T. Aoyagi, Masahiro Fujita, Tohru Moto-Oka

Proceedings of the Logic Programming '85, 1985

Memory Management Algorithms in Pipeline Merge Sorter.

Masaru Kitsuregawa, Shinya Fushimi, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the Database Machines, 1985

Multidimensional Clustering Techniques for Large Relational Database Machines.

Shinya Fushimi, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the Foundations of Data Organization, 1985

1984

Highly Parallel Inference Engine PIE: Goal Rewriting Model and Machine Architecture.

Atsuhiro Goto, Hidehiko Tanaka, Tohru Moto-Oka

New Gener. Comput., 1984

Fifth-Generation Computer Systems: A Japanese Project.

Tohru Moto-Oka, Harold S. Stone

Computer, 1984

The Architecture of a Parallel Inference Engine - PIE.

Tohru Moto-Oka, Hidehiko Tanaka, Hitoshi Aida, Keiji Hirata, Tsutomu Maruyama

Proceedings of the International Conference on Fifth Generation Computer Systems, 1984

Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog.

Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the International Conference on Fifth Generation Computer Systems, 1984

1983

On the Founding of This Journal.

Tohru Moto-Oka

New Gener. Comput., 1983

Application of Hash to Data Base Machine and Its Architecture.

Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka

New Gener. Comput., 1983

Temporal Logic Based Hardware Description and Its Verification with Prolog.

Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka

New Gener. Comput., 1983

A Prolog Extension for Handling Negative Knowledge.

Hitoshi Aida, Hidehiko Tanaka, Tohru Moto-Oka

New Gener. Comput., 1983

Overview to the Fifth Generation Computer System Project

Tohru Moto-Oka

Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

The Architectures in the Fifth Generation Computers.

Tohru Moto-Oka, Kazuhiro Fuchi

Proceedings of the Information Processing 83, 1983

1982

Relational Algebra Machine GRACE.

Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka

Proceedings of the RIMS Symposium on Software Science and Engineering, 1982

1975

Logic design system in Japan.

Tohru Moto-Oka, Tadashi Kurachi, Tsutomu Shiino, Masakatsu Sugimoto

Proceedings of the 12th Design Automation Conference, 1975

1960

Esaki Diode High-Speed Logical Circuits.

Eiichi Goto, Kenro Murata, Kisaburo Nakazawa, Keisuke Nakagawa, Tohru Moto-Oka, Yasushi Miatsu-Oka, Yoshihiro Ishibashi, Haruhisa Ishida, Takashi Soma, Eiiti Wada

IRE Trans. Electron. Comput., 1960