Kisaburo Nakazawa

According to our database, Kisaburo Nakazawa authored at least 11 papers between 1960 and 1999.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1999

CP-PACS: A massively parallel processor at the University of Tsukuba.

Kisaburo Nakazawa, Hiroshi Nakamura, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita

Parallel Comput., 1999

1997

CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations.

Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa

Proceedings of the 11th international conference on Supercomputing, 1997

Advanced processor design using hardware description language AIDL.

Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Adaptive routing technique on hypercrossbar network and its evaluation.

Taisuke Boku, Kisaburo Nakazawa, Hiroshi Nakamura, Takeshi Sone, Takeshi Mishima, Ken'ichi Itakura

Syst. Comput. Jpn., 1996

1995

A superscalar RISC processor with pseudo vector processing feature.

Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers.

Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993

A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.

Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita

Proceedings of the 7th international conference on Supercomputing, 1993

1992

Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline.

Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe

Proceedings of the Proceedings Supercomputing '92, 1992

1964

Very high speed serial and serial-parallel computers HITAC 5020 and 5020E.

Kenro Murata, Kisaburo Nakazawa

Proceedings of the 1964 fall joint computer conference, part I, 1964

1962

A Tunnel-Diode High-Speed Memory.

S. Takahashi, Kisaburo Nakazawa, Kenro Murata, Osamu Ishii

Proceedings of the Information Processing, Proceedings of the 2nd IFIP Congress 1962, Munich, Germany, August 27, 1962

1960

Esaki Diode High-Speed Logical Circuits.

Eiichi Goto, Kenro Murata, Kisaburo Nakazawa, Keisuke Nakagawa, Tohru Moto-Oka, Yasushi Miatsu-Oka, Yoshihiro Ishibashi, Haruhisa Ishida, Takashi Soma, Eiiti Wada

IRE Trans. Electron. Comput., 1960