William J. Starke

Orcid: 0000-0002-5668-585X

According to our database1, William J. Starke authored at least 17 papers between 1996 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
IBM's POWER10 Processor.
IEEE Micro, 2021


2020
Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

IBM's POWER10 Processor.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2019
IBM's Next Generation POWER Processor.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

2018
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI.
IBM J. Res. Dev., 2018

IBM POWER9 memory architectures for optimized systems.
IBM J. Res. Dev., 2018

2017
IBM Power9 Processor Architecture.
IEEE Micro, 2017

2015
The cache and memory subsystems of the IBM POWER8 processor.
IBM J. Res. Dev., 2015

Transactional memory support in the IBM POWER8 processor.
IBM J. Res. Dev., 2015

2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2011
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
IEEE J. Solid State Circuits, 2011

2010
Power7: IBM's Next-Generation Server Processor.
IEEE Micro, 2010

The implementation of POWER7<sup>TM</sup>: A highly parallel and scalable multi-core high-end server processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
POWER7: IBM's next generation, balanced POWER server chip.
Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

2007
IBM POWER6 microarchitecture.
IBM J. Res. Dev., 2007

1996
Real-Time Trace Generation.
Int. J. Comput. Simul., 1996


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