Euisik Yoon

According to our database1, Euisik Yoon authored at least 34 papers between 2000 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2019
Microneedle Penetrating Array with Axon-Sized Dimensions for Cuff-less Peripheral Nerve Interfacing.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019

2018
A High-Resolution Opto-Electrophysiology System With a Miniature Integrated Headstage.
IEEE Trans. Biomed. Circuits Syst., 2018

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems.
Sensors, 2018

Modular 128-Channel Δ-ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems.
IEEE J. Solid State Circuits, 2018

Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals.
IEEE J. Solid State Circuits, 2018

A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
A miniature headstage for high resolution closed-loop optogenetics.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Chronic In Vivo Evaluation of PEDOT/CNT for Stable Neural Recordings.
IEEE Trans. Biomed. Eng., 2016

A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression.
IEEE J. Solid State Circuits, 2016

Efficient assembly of multi-color fiberless optoelectrodes with on-board light sources for neural stimulation and recording.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems.
IEEE Trans. Biomed. Circuits Syst., 2015

An Energy/Illumination-Adaptive CMOS Image Sensor With Reconfigurable Modes of Operations.
IEEE J. Solid State Circuits, 2015

Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ analog front-end architecture with 4.84fJ/C-s·mm<sup>2</sup> energy-area product.
Proceedings of the Symposium on VLSI Circuits, 2015

Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression.
Proceedings of the Symposium on VLSI Circuits, 2015

12.3 PWM buck converter with >80% PCE in 45μA-to-4mA loads using analog-digital hybrid control for impiantale biomedical systems.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 3.4-µW Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging.
IEEE J. Solid State Circuits, 2014

A 3-D Camera With Adaptable Background Light Suppression Using Pixel-Binning and Super-Resolution.
IEEE J. Solid State Circuits, 2014

7.2 243.3pJ/pixel bio-inspired time-stamp-based 2D optic flow sensor for artificial compound eyes.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 3.4µW CMOS image sensor with embedded feature-extraction algorithm for motion-triggered object-of-interest imaging.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Label-Free CMOS Bio Sensor With On-Chip Noise Reduction Scheme for Real-Time Quantitative Monitoring of Biomolecules.
IEEE Trans. Biomed. Circuits Syst., 2012

A 4 µW/Ch Analog Front-End Module With Moderate Inversion and Power-Scalable Sampling Operation for 3-D Neural Microsystems.
IEEE Trans. Biomed. Circuits Syst., 2012

A 1.36μW adaptive CMOS image sensor with reconfigurable modes of operation from available energy/illumination for distributed wireless sensor network.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 0.5V 20fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

The first neural probe integrated with light source (blue laser diode) for optical stimulation and electrical recording.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

A dual-shank neural probe integrated with double waveguides on each shank for optogenetic applications.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

A 1.5V 120nW CMOS programmable monolithic reference generator for wireless implantable system.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Design of double layer printed spiral coils for wirelessly-powered biomedical implants.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

A 8.6 μW 3-bit programmable gain amplifier for multiplexed-input neural recording systems.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

2008
A CMOS Fingerprint System-on-a-Chip With Adaptable Pixel Networks and Column-Parallel Processors for Image Enhancement and Recognition.
IEEE J. Solid State Circuits, 2008

2007
A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network.
IEEE J. Solid State Circuits, 2007

A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects in Region-of-Interest and Suppressing Motion Blur.
IEEE J. Solid State Circuits, 2007

Sensors and MEMS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Spatial-Temporal Multi-Resolution CMOS Image Sensor with Adaptive Frame Rates for Moving Objects in the Region-of-Interest.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2000
A new adder scheme with reduced P, G signal generations using redundant binary number system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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