Michael P. Flynn
Orcid: 0000-0001-5070-7512Affiliations:
- University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA
According to our database1,
Michael P. Flynn
authored at least 109 papers
between 1996 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE J. Solid State Circuits, April, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer.
IEEE J. Solid State Circuits, 2023
A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 0.024mm² 84.2dB-SNDR 1MHz-BW 3<sup>rd</sup>-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM).
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
IEEE J. Solid State Circuits, 2021
IEEE J. Solid State Circuits, 2021
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM.
IEEE J. Solid State Circuits, 2021
IEEE J. Solid State Circuits, 2021
A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping.
Proceedings of the 47th ESSCIRC 2021, 2021
A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
IEEE J. Solid State Circuits, 2020
An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
9.4 A 4<sup>th</sup>-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4<sup>th</sup>-Order Noise-Shaping SAR ADC.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS.
IEEE J. Solid State Circuits, 2018
Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System.
IEEE J. Solid State Circuits, 2018
A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 36.3-to-38.2GHz -216dBc/Hz<sup>2</sup> 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging.
IEEE J. Solid State Circuits, 2017
2016
A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression.
IEEE J. Solid State Circuits, 2016
A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC.
IEEE J. Solid State Circuits, 2015
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers.
IEEE J. Solid State Circuits, 2015
Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression.
Proceedings of the Symposium on VLSI Circuits, 2015
26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 28.5-33.5GHz fractional-N PLL using a 3<sup>rd</sup> order noise shaping time-to-digital converter with 176fs resolution.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management.
IEEE J. Solid State Circuits, 2014
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEEE J. Solid State Circuits, 2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
2010
A 9-bit, 14 μW and 0.06 mm <sup>2</sup> Pulse Position Modulation ADC in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010
A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC.
IEEE J. Solid State Circuits, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme.
IEEE J. Solid State Circuits, 2008
A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE J. Solid State Circuits, 2007
A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
A new transponder architecture with on-chip ADC for long-range telemetry applications.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
An RF powered, wireless temperature sensor in quarter micron CMOS.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
2002
IEEE J. Solid State Circuits, 2002
2001
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator.
IEEE J. Solid State Circuits, 2001
2000
A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
IEEE J. Solid State Circuits, 1998
1996
IEEE J. Solid State Circuits, 1996