Jeffrey Fredenburg

According to our database1, Jeffrey Fredenburg authored at least 13 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Synchronous Die-to-Die Signaling Using Aeonic Connect.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2017
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging.
IEEE J. Solid State Circuits, 2017

2016
A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression.
IEEE J. Solid State Circuits, 2016

A 16-channel noise-shaping machine learning analog-digital interface.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression.
Proceedings of the Symposium on VLSI Circuits, 2015

ADC trends and impact on SAR ADC architecture and analysis.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management.
IEEE J. Solid State Circuits, 2014

An N-path filter enhanced low phase noise ring VCO.
Proceedings of the Symposium on VLSI Circuits, 2014

2012
Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC.
IEEE J. Solid State Circuits, 2012

A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders.
Proceedings of the Symposium on VLSI Circuits, 2012

A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010


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