Fabio Padovan

Orcid: 0000-0002-6397-1002

According to our database¹, Fabio Padovan authored at least 19 papers between 2012 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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On csauthors.net:

Bibliography

2024

Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, January, 2024

2023

A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

2022

A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021

A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 47th ESSCIRC 2021, 2021

2020

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects.

[BibT_eX]

[DOI]

Alessandro Franceschin

IEEE J. Solid State Circuits, 2020

2019

A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion.

[BibT_eX]

[DOI]

Alessandro Franceschin

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS.

[BibT_eX]

[DOI]

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018

On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators.

[BibT_eX]

[DOI]

Alessandro Franceschin

Fabio Padovan

Roberto Nonis

Andrea Bevilacqua

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016

A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015

Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

2014

A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS.

[BibT_eX]

[DOI]

Fabio Padovan

Andrea Bevilacqua

Andrea Neviani

Proceedings of the ESSCIRC 2014, 2014

2012

A SiGe bipolar VCO for backhaul E-band communication systems.

[BibT_eX]

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

Fabio Padovan

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