Feida Wang

According to our database¹, Feida Wang authored at least 3 papers between 2023 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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2025

A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

A 0.55-mm<sup>2</sup> 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture.

[BibT_eX]

[DOI]

Microelectron. J., February, 2024

2023

An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Feida Wang

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