Ruixue Ding

Orcid: 0009-0006-8632-8032

According to our database1, Ruixue Ding authored at least 52 papers between 2013 and 2024.

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Bibliography

2024
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs<sub>rms</sub> Integrated Jitter and -250.8-dB FOM<sub>PLL</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

Let LLMs Take on the Latest Challenges! A Chinese Dynamic Question Answering Benchmark.
CoRR, 2024

Geo-Encoder: A Chunk-Argument Bi-Encoder Framework for Chinese Geographic Re-Ranking.
Proceedings of the 18th Conference of the European Chapter of the Association for Computational Linguistics, 2024

2023
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

16-Cell stackable battery monitoring and management integrated circuit for electric vehicles.
Microelectron. J., 2023

GeoGLUE: A GeoGraphic Language Understanding Evaluation Benchmark.
CoRR, 2023

A Multi-Modal Geographic Pre-Training Method.
CoRR, 2023

MGeo: Multi-Modal Geographic Language Model Pre-Training.
Proceedings of the 46th International ACM SIGIR Conference on Research and Development in Information Retrieval, 2023

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

Adversarial Self-Attention for Language Understanding.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Radio frequency analog-to-digital converters: Systems and circuits review.
Microelectron. J., 2022

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations.
IEEE J. Solid State Circuits, 2022

Forging Multiple Training Objectives for Pre-trained Language Models via Meta-Learning.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2022, 2022

2021
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs.
Microelectron. J., 2021

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS.
J. Circuits Syst. Comput., 2021

Knowledge-aware Named Entity Recognition with Alleviating Heterogeneity.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS.
IEEE Trans. Circuits Syst., 2020

A 7b 400 ​MS/s pipelined SAR ADC in 65 ​nm CMOS.
Microelectron. J., 2020

2019
A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC.
J. Circuits Syst. Comput., 2019

A High Gain, 808MHz GBW Four-Stage OTA in 65nm CMOS.
J. Circuits Syst. Comput., 2019

Better Modeling of Incomplete Annotations for Named Entity Recognition.
Proceedings of the 2019 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, 2019

A Neural Multi-digraph Model for Chinese NER with Gazetteers.
Proceedings of the 57th Conference of the Association for Computational Linguistics, 2019

2018
A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS.
Microelectron. J., 2018

Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs.
J. Circuits Syst. Comput., 2018

Inductance of Different Profiles of Through Glass Vias based on magnetic flux density.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Event Extraction with Deep Contextualized Word Representation and Multi-attention Layer.
Proceedings of the Advanced Data Mining and Applications - 14th International Conference, 2018

2017
A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage.
Microelectron. J., 2017

Analysis and optimal distribution scheme for SAR-VCO ADCs.
Microelectron. J., 2017

2016
A low-distortion CMOS analogue voltage follower for high-speed ADCs.
Microelectron. J., 2016

Analysis of propagation delay and repeater insertion in single-walled carbon nanotube bundle interconnects.
Microelectron. J., 2016

2015
A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS.
Microelectron. J., 2015

Calibration algorithm for 16-bit voltage-mode R-2R DAC.
Microelectron. J., 2015

Strategy for SAR ADC with 87.5% area saving and 99.4% switching energy reduction over conventional approach.
IEICE Electron. Express, 2015

Ultra-low energy switching scheme for SAR ADC.
IEICE Electron. Express, 2015

2014
Capacitance characterization of tapered through-silicon-via considering MOS effect.
Microelectron. J., 2014

Temperature properties of the parasitic resistance of through-silicon vias (TSVs) in high-frequency 3-D ICs.
IEICE Electron. Express, 2014

2013
Thermo-mechanical performance of Cu and SiO<sub>2</sub> filled coaxial through-silicon-via (TSV).
IEICE Electron. Express, 2013

Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV).
IEICE Electron. Express, 2013

Reduction of signal reflection in high-frequency three-dimensional (3D) integration circuits.
IEICE Electron. Express, 2013


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