Dengquan Li

According to our database, Dengquan Li authored at least 30 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 0.55-mm² 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture.

Jiale Ding, Yukai Huang, Hao Zhang, Tian Feng, Feida Wang, Dengquan Li, Zhangming Zhu

Microelectron. J., February, 2024

A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.

Hongzhi Liang, Shubin Liu, Ruixue Ding, Yi Shen, Dengquan Li, Zhangming Zhu

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.

Dengquan Li, Longsheng Wang, Yi Shen, Shubin Liu, Zhangming Zhu

IEEE Trans. Instrum. Meas., 2024

2023

An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.

Xin Zhao, Dengquan Li, Feida Wang, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.

Yi Shen, Junyan Hao, Shubin Liu, Zeshuai An, Dengquan Li, Ruixue Ding, Zhangming Zhu

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS.

Dengquan Li, Xin Zhao, Yi Shen, Shubin Liu, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.

Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs.

Dengquan Li, Lei Zhao, Longsheng Wang, Yi Shen, Zhangming Zhu

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs.

Depeng Sun, Ruixue Ding, Feng Bu, Hongzhi Liang, Dengquan Li, Yuhua Liang, Shubin Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS.

Maliang Liu, Chenxi Zhang, Shubin Liu, Dengquan Li

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS.

Henghui Mao, Dengquan Li, Shubin Liu

Microelectron. J., 2022

Radio frequency analog-to-digital converters: Systems and circuits review.

Dengquan Li, Xin Zhao, Shubin Liu, Maliang Liu, Ruixue Ding, Yuhua Liang, Zhangming Zhu

Microelectron. J., 2022

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration.

Yukai Huang, Jiale Ding, Dengquan Li, Xin Zhao, Shubin Liu, Yi Shen, Zhangming Zhu

Microelectron. J., 2022

Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs.

Jiale Ding, Yukai Huang, Dengquan Li, Shubin Liu, Yi Shen, Zhangming Zhu

Circuits Syst. Signal Process., 2022

A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower.

Tian Feng, Dengquan Li, Jiale Ding, Shubin Liu, Yi Shen, Zhangming Zhu

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

A TD-ADC for IR-UWB Radars With Equivalent Sampling Technology and 8-GS/s Effective Sampling Rate.

Zhangming Zhu, Yu Zhu, Dengquan Li, Maliang Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs.

Dengquan Li, Maliang Liu, Shubin Liu, Yuhua Liang, Ruixue Ding

Microelectron. J., 2021

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS.

Lei Zhao, Dengquan Li, Henghui Mao, Ruixue Ding, Zhangming Zhu

J. Circuits Syst. Comput., 2021

27.1 A 250kHz-BW 93dB-SNDR 4^th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering.

Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application.

Maliang Liu, Dengquan Li, Zhangming Zhu

IEEE Trans. Circuits Syst. II Express Briefs, 2020

An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS.

Dengquan Li, Maliang Liu, Lei Zhao, Henghui Mao, Ruixue Ding, Zhangming Zhu

IEEE Trans. Circuits Syst., 2020

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration.

Dengquan Li, Zhangming Zhu, Jiaxin Liu, Haoyu Zhuang, Yintang Yang, Nan Sun

IEEE J. Solid State Circuits, 2020

2019

A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration.

Dengquan Li, Zhangming Zhu, Ruixue Ding, Maliang Liu, Yintang Yang, Nan Sun

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration.

Dengquan Li, Jiaxin Liu, Haoyu Zhuang, Zhangming Zhu, Yintang Yang, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS.

Dengquan Li, Zhangming Zhu, Ruixue Ding, Yintang Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS.

Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu

Microelectron. J., 2018

A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation.

Dengquan Li, Ruixue Ding, Zhangming Zhu, Yintang Yang

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2016

A background fast convergence algorithm for timing skew in time-interleaved ADCs.

Dengquan Li, Zhangming Zhu, Liang Zhang, Yintang Yang

Microelectron. J., 2016

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS.

Liang Zhang, Dengquan Li, Zhangming Zhu, Yintang Yang

J. Circuits Syst. Comput., 2016

2015

An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS.

Dengquan Li, Liang Zhang, Zhangming Zhu, Yintang Yang

J. Circuits Syst. Comput., 2015