Francisco J. Andujar

Miguel Sánchez de la Rosa

Pierre-Axel Lagadec

J. Supercomput., March, 2025

Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application.

[BibT_eX]

[DOI]

IEEE Access, 2025

2024

Applying machine learning to assess emotional reactions to video game content streamed on Spanish Twitch channels.

[BibT_eX]

[DOI]

Comput. Speech Lang., 2024

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL.

[BibT_eX]

[DOI]

CoRR, 2024

Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools.

[BibT_eX]

[DOI]

CoRR, 2024

Quality-of-Service Provision for BXI3-Based Interconnection Networks.

[BibT_eX]

[DOI]

Gabriel Gomez-Lopez

Francisco J. Alfaro

Pierre-Axel Lagadec

Proceedings of the IEEE Symposium on High-Performance Interconnects, 2024

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2024: Parallel Processing Workshops, 2024

2023

Supporting efficient overlapping of host-device operations for heterogeneous programming with CtrlEvents.

[BibT_eX]

[DOI]

Yuri Torres

Arturo González-Escribano

Diego R. Llanos

J. Parallel Distributed Comput., September, 2023

Extending the VEF traces framework to model data center network workloads.

[BibT_eX]

[DOI]

Miguel Sánchez de la Rosa

J. Supercomput., 2023

Energy efficient HPC network topologies with on/off links.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2023

Open SYCL on heterogeneous GPU systems: A case of study.

[BibT_eX]

[DOI]

Rocío Carratalá-Sáez

Arturo González-Escribano

Yuri Torres

Diego R. Llanos

CoRR, 2023

2022

Providing quality of service in omni-path networks.

[BibT_eX]

[DOI]

Gaspar Mora

J. Supercomput., 2022

2021

Enabling Quality of Service Provision in Omni-Path Switches.

[BibT_eX]

[DOI]

Comput. Math. Methods, November, 2021

Efficient heterogeneous programming with FPGAs using the Controller model.

[BibT_eX]

[DOI]

Gabriel Rodriguez-Canal

Yuri Torres

Arturo González-Escribano

J. Supercomput., 2021

A methodology to enable QoS provision on InfiniBand hardware.

[BibT_eX]

[DOI]

J. Supercomput., 2021

QoS provision in hierarchical and non-hierarchical switch architectures.

[BibT_eX]

[DOI]

Francisco J. Andujar-Munoz

J. Parallel Distributed Comput., 2021

2019

POWAR: Power-Aware Routing in HPC Networks with On/Off Links.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2019

Speeding up exascale interconnection network simulations with the VEF3 trace framework.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

Energy efficient torus networks with on/off links.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

Constructing virtual 5-dimensional tori out of lower-dimensional network cards.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2019

2018

VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018

Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018

2017

Applying search algorithms to obtain the optimal configuration of nDT torus nodes.

[BibT_eX]

[DOI]

Juan A. Villar-Ortiz

José Luis Sánchez Garcia

Francisco J. Alfaro-Cortes

Concurr. Comput. Pract. Exp., 2017

A Case Study on Implementing Virtual 5D Torus Networks Using Network Components of Lower Dimensionality.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2017

2016

An open-source family of tools to reproduce MPI-based workloads in interconnection network simulators.

[BibT_eX]

[DOI]

Francisco J. Andujar-Munoz

J. Supercomput., 2016

Adaptive Routing for N-Dimensional Twin Torus.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

2015

Optimizing the configuration of combined high-radix switches.

[BibT_eX]

[DOI]

J. Supercomput., 2015

N-Dimensional Twin Torus Topology.

[BibT_eX]

[DOI]

Juan A. Villar-Ortiz

IEEE Trans. Computers, 2015

VEF Traces: A Framework for Modelling MPI Traffic in Interconnection Network Simulators.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Cluster Computing, 2015

2014

Formalization and configuration methodology for high-radix combined switches.

[BibT_eX]

[DOI]

J. Supercomput., 2014

Building 3D Torus Using Low-Profile Expansion Cards.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Optimal Configuration for N-Dimensional Twin Torus Networks.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 13th International Symposium on Network Computing and Applications, 2014

Deadlock-free routing mechanism for 3D twin torus networks.

[BibT_eX]

[DOI]

Proceedings of the 8th International Workshop on Interconnection Network Architecture, 2014

2013

Obtaining the optimal configuration of high-radix Combined switches.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2013

2012

Optimal Configuration of High-Radix Combined Switches.

[BibT_eX]

[DOI]

Juan A. Villar

Francisco J. Andujar

Proceedings of the 20th Euromicro International Conference on Parallel, 2012

2011

Evaluation of an Alternative for Increasing Switch Radix.

[BibT_eX]

[DOI]

Juan A. Villar

Francisco J. Andujar

Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011

Self-related traces: An alternative to full-system simulation for NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

C-Switches: Increasing Switch Radix with Current Integration Scale.

[BibT_eX]

[DOI]

Juan A. Villar

Francisco J. Andujar