Gabriel Rodriguez-Canal

Orcid: 0009-0005-0511-3922

According to our database1, Gabriel Rodriguez-Canal authored at least 13 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Lifting to tensors when compiling scientific computing workloads for AI Engines.
CoRR, May, 2026

Towards Scheduling of Pipelined Dataflow Graphs in MLIR.
Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026

Towards Compiler-Driven Dynamic Partial Reconfiguration with MLIR.
Proceedings of the 34th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2026

2025
An MLIR pipeline for offloading Fortran to FPGAs via OpenMP.
Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, 2025

Programmer productivity and performance on AMD's AI Engines: Offloading Fortran intrinsics via MLIR a case-study.
Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, 2025

Seamless Acceleration of Fortran Intrinsics via AMD AI Engines.
Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2025

2024
A shared compilation stack for distributed-memory parallelism in stencil DSLs.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Task-based preemptive scheduling on FPGAs leveraging partial reconfiguration.
Concurr. Comput. Pract. Exp., 2023

Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
Programming Abstractions for Preemptive Scheduling on FPGAs Using Partial Reconfiguration.
Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022

FPGAs in Supercomputers: Performance Through Dataflow Programming and Flexibility.
Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022

2021
Efficient heterogeneous programming with FPGAs using the Controller model.
J. Supercomput., 2021


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