Pedro López

Affiliations:
  • Universitat Politècnica de València, Spain


According to our database1, Pedro López authored at least 141 papers between 1993 and 2021.

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Bibliography

2021
Improving the Robustness of Redundant Execution with Register File Randomization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2019
POWAR: Power-Aware Routing in HPC Networks with On/Off Links.
ACM Trans. Archit. Code Optim., 2019

Energy efficient torus networks with on/off links.
J. Parallel Distributed Comput., 2019

2018
Teaching high-performance service in a cluster computing course.
J. Parallel Distributed Comput., 2018

Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes.
Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018

2017
XOR-based HoL-blocking reduction routing mechanisms for direct networks.
Parallel Comput., 2017

On a course on computer cluster configuration and administration.
J. Parallel Distributed Comput., 2017

A fault-tolerant routing strategy for <i>k</i>-ary <i>n</i>-direct <i>s</i>-indirect topologies based on intermediate nodes.
Concurr. Comput. Pract. Exp., 2017

2016
A Family of Fault-Tolerant Efficient Indirect Topologies.
IEEE Trans. Parallel Distributed Syst., 2016

The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks.
J. Supercomput., 2016

Embedded GPU and multicore processors for emotional-based mobile robotic agents.
Future Gener. Comput. Syst., 2016

A New Fault-Tolerant Routing Methodology for KNS Topologies.
Proceedings of the 2nd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era HiPINEB@HPCA 2016, 2016

2015
A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies.
J. Supercomput., 2015

Design of Hybrid Second-Level Caches.
IEEE Trans. Computers, 2015

Power consumption management in fat-tree interconnection networks.
Parallel Comput., 2015

XORAdap: A HoL-Blocking Aware Adaptive Routing Algorithm.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Speeding-up the fault-tolerance analysis of interconnection networks.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

Using GPU and SIMD Implementations to Improve Performance of Robotic Emotional Processes.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014
Efficient Register Renaming and Recovery for High-Performance Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

HoL-Blocking Avoidance Routing Algorithms in Direct Topologies.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013
Hardware-Based Generation of Independent Subtraces of Instructions in Clustered Processors.
IEEE Trans. Computers, 2013

Deterministic Routing with HoL-Blocking-Awareness for Direct Topologies.
Proceedings of the International Conference on Computational Science, 2013

Topic 13: High-Performance Networks and Communication - (Introduction).
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions.
IEEE Trans. Parallel Distributed Syst., 2012

A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms.
IEEE Trans. Parallel Distributed Syst., 2012

Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches.
IEEE Trans. Computers, 2012

Progressive Congestion Management Based on Packet Marking and Validation Techniques.
IEEE Trans. Computers, 2012

Combining recency of information with selective random and a victim cache in last-level caches.
ACM Trans. Archit. Code Optim., 2012

A New Family of Hybrid Topologies for Large-Scale Interconnection Networks.
Proceedings of the 11th IEEE International Symposium on Network Computing and Applications, 2012

IODET: A HoL-blocking-aware Deterministic Routing Algorithm for Direct Topologies.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Analyzing the optimal ratio of SRAM banks in hybrid caches.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Towards an Efficient Fat-Tree like Topology.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2011
Routing (Including Deadlock Avoidance).
Proceedings of the Encyclopedia of Parallel Computing, 2011

How to reduce packet dropping in a bufferless NoC.
Concurr. Comput. Pract. Exp., 2011

MRU-Tour-based Replacement Algorithms for Last-Level Caches.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Power saving in regular interconnection networks.
Parallel Comput., 2010

A Scalable and Early Congestion Management Mechanism for MINs.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

Out-of-order retirement of instructions in sequentially consistent multiprocessors.
Proceedings of the 28th International Conference on Computer Design, 2010

Exploiting subtrace-level parallelism in clustered processors.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

FT<sup>2</sup>EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals.
IEEE Trans. Parallel Distributed Syst., 2009

A Complexity-Effective Out-of-Order Retirement Microarchitecture.
IEEE Trans. Computers, 2009

Power Reduction In Advanced Embedded IPC Processors.
Intell. Autom. Soft Comput., 2009

An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Boosting single-thread performance in multi-core systems through fine-grain multi-threading.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery.
Proceedings of the 27th International Conference on Computer Design, 2009

Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading.
Proceedings of the PACT 2009, 2009

2008
Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network.
IEEE Comput. Archit. Lett., 2008

Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

RUFT: Simplifying the Fat-Tree Topology.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

An Efficient Switching Technique for NoCs with Reduced Buffer Requirements.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot.
Proceedings of the Euro-Par 2008, 2008

Reducing Packet Dropping in a Bufferless NoC.
Proceedings of the Euro-Par 2008, 2008

On the Influence of the Packet Marking and Injection Control Schemes in Congestion Management for MINs.
Proceedings of the Euro-Par 2008, 2008

2007
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

Congestion Management in MINs through Marked and Validated Packets.
Proceedings of the 15th Euromicro International Conference on Parallel, 2007

Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Deterministic versus Adaptive Routing in Fat-Trees.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Leakage Current Reduction in Data Caches on Embedded Systems.
Proceedings of the 2007 International Conference on Intelligent Pervasive Computing, 2007

Power-Aware Fat-Tree Networks Using On/Off Links.
Proceedings of the High Performance Computing and Communications, 2007

VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
A Routing Methodology for Achieving Fault Tolerance in Direct Networks.
IEEE Trans. Computers, 2006

An Efficient Fault-Tolerant Routing Strategy for Tori and Meshes.
Scalable Comput. Pract. Exp., 2006

FIR: An efficient routing strategy for tori and meshes.
J. Parallel Distributed Comput., 2006

Applying the zeros switch-off technique to reduce static energy in data caches.
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

Dynamic power saving in fat-tree interconnection networks using on/off links.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

On the Influence of the Selection Function on the Performance of Fat-Trees.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Towards an efficient switch architecture for high-radix switches.
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

2005
A Family of Mechanisms for Congestion Control in Wormhole Networks.
IEEE Trans. Parallel Distributed Syst., 2005

Enforcing in-order packet delivery in system area networks with adaptive routing.
J. Parallel Distributed Comput., 2005

A Memory-Effective Fault-Tolerant Routing Strategy for Direct Interconnection Networks.
Proceedings of the 4th International Symposium on Parallel and Distributed Computing (ISPDC 2005), 2005

In-Order Packet Delivery in Interconnection Networks using Adaptive Routing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A Memory-Effective Routing Strategy for Regular Interconnection Networks.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Power Saving in Regular Interconnection Networks Built with High-Degree Switches.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori.
IEEE Comput. Archit. Lett., 2004

A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2004

A Transition-Based Fault-Tolerant Routing Methodology for InfiniBand Networks.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

An Effective Fault-Tolerant Routing Methodology for Direct Networks.
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

LASH-TOR: A Generic Transition-Oriented Routing Algorithm.
Proceedings of the 10th International Conference on Parallel and Distributed Systems, 2004

A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks.
Proceedings of the High Performance Computing, 2004

Reducing Power Consumption in Interconnection Networks by Dynamically Adjusting Link Width.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
FC3D: Flow Control-Based Distributed Deadlock Detection Mechanism for True Fully Adaptive Routing in Wormhole Networks.
IEEE Trans. Parallel Distributed Syst., 2003

Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing.
IEEE Trans. Computers, 2003

Supporting adaptive routing in IBA switches.
J. Syst. Archit., 2003

Supporting Adaptive Routing in InfiniBand Networks.
Proceedings of the 11th Euromicro Workshop on Parallel, 2003

Performance Evaluation of COWs under Real Parallel Application.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Supporting Fully Adaptive Routing in InfiniBand Networks.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Routing in InfiniBandTM Torus Network Topologie.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBand<sup>TM</sup>.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

A Robust Mecahnism for Congestion Control: INC.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
Boosting the Performance of Myrinet Networks.
IEEE Trans. Parallel Distributed Syst., 2002

Removing the Latency Overhead of the ITB Mechanism in COWs with Source Routing.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

Increasing the Adaptivity of Routing Algorithms for k-ary n-cubes.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

Improving InfiniBand Routing through Multiple Virtual Networks.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Avoiding Network Congestion with Local Information.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

Evaluation of Routing Algorithms for InfiniBand Networks (Research Note).
Proceedings of the Euro-Par 2002, 2002

Congestion Control Based on Transmission Times.
Proceedings of the Euro-Par 2002, 2002

2001
A Cost-Effective Approach to Deadlock Handling in Wormhole Networks.
IEEE Trans. Parallel Distributed Syst., 2001

A Congestion Control Mechanism for Wormhole Networks.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

A First Implementation of In-Transit Buffers on Myrinet GM Software.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Deadlock-Free Routing in InfiniBand through Destination Renaming.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

2000
On the Influence of the Selection Function on the Performance of Networks of Workstations.
Proceedings of the High Performance Computing, Third International Symposium, 2000

Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing.
Proceedings of the High Performance Computing, Third International Symposium, 2000

Improving Routing Performance in Myrinet Networks.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

A Simple and Efficient Mechanism to Prevent Saturation in Wormhole Networks.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Performance evaluation of a new routing strategy for irregular networks with source routing.
Proceedings of the 14th international conference on Supercomputing, 2000

Improving the Performance of Regular Networks with Source Routing.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

1999
Optimizing network throughput: optimal versus robust design.
Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation.
Proceedings of the International Conference on Parallel Processing 1999, 1999

Impact of Buffer Size on the Efficiency of Deadlock Detection.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
A cost-effective methodology for the evaluation of interconnection networks.
J. Syst. Archit., 1998

A lab course on computer architecture.
Proceedings of the 1998 workshop on Computer architecture education, 1998

DRIL: Dynamically Reduced Message Injection Limitation Mechanism for Wormhole Networks.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

Edinet: An Execution Driven Interconnection Network Simulator for DSM Systems.
Proceedings of the Computer Performance Evaluation: Modelling Techniques and Tools, 1998

1997
On the Reduction of Deadlock Frequency by Limiting Message Injection in Wormhole Networks.
Proceedings of the Parallel Computer Routing and Communication, 1997

Deadlock- and Livelock-Free Routing Protocols for Wave Switching.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Software-Based Deadlock Recovery Technique for True Fully Adaptive Routing in Wormhole Networks.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

LIFE: a limited injection, fully adaptive, recovery-based routing algorithm.
Proceedings of the Fourth International on High-Performance Computing, 1997

Efficient Adaptive Routing in Networks of Workstations with Irregular Topology.
Proceedings of the Communication and Architectural Support for Network-Based Parallel Computing, 1997

1996
Interconnection Network Design: A Statistical Analysis of Interactions between Factors.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

A High Performance Router Architecture for Interconnection Networks.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

1995
Deadlock-Free Fully-Adaptive Minimal Routing Algorithms: Limitations and Solutions.
Comput. Artif. Intell., 1995

1994
Bandwidth Requirements For Wormhole Switches: A Simple And Efficient Design.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

Performance Evaluation of Adaptive Routing Algorithms for k-ary-n-cubes.
Proceedings of the Parallel Computer Routing and Communication, 1994

Highly adaptive wormhole routing algorithms for N-dimensional torus.
Proceedings of the Workshop on Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994

1993
Deadlock-Free Adaptive Routing Algorithms for the 3D-Torus: Limitations and Solutions.
Proceedings of the PARLE '93, 1993


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