Francisco-Javier Veredas

According to our database, Francisco-Javier Veredas authored at least 9 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2018

FPGA Placement Improvement Using a Genetic Algorithm and the Routing Algorithm as a Cost Function.

Francisco-Javier Veredas, Enrique J. Carmona

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2006

Regular Routing Architecture for a LUT-based MPGA.

Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

LUT-based MPGAs for fast turnaround time conversion flow.

Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power estimation of a LUT-based MPGA.

Francisco-Javier Veredas, Hans-Jörg Pfleiderer

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.

Francisco-Javier Veredas, Hans-Jörg Pfleiderer

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.

Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.

Francisco-Javier Veredas, Jordi Carrabina

Proceedings of the Integrated Circuit and System Design, 2005

Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.

Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.

Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005