Michael Scheppler

According to our database1, Michael Scheppler authored at least 6 papers between 2003 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2009
Non-Volatile Memories for Removable Media.
Proc. IEEE, 2009

2006
Regular Routing Architecture for a LUT-based MPGA.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

LUT-based MPGAs for fast turnaround time conversion flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2003
A New Reconfigurable Architecture for Single Cycle Context Switching.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003


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