Bingfeng Mei

According to our database1, Bingfeng Mei authored at least 17 papers between 2001 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors.
Signal Processing Systems, 2010

2009
Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2009

Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor.
Microprocess. Microsystems, 2009

2008
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder.
Signal Processing Systems, 2008

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

2007
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
Hardware and a Tool Chain for ADRES.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Architecture Exploration for a Reconfigurable Architecture Template.
IEEE Design & Test of Computers, 2005

Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Design Style Case Study for Embedded Multi Media Compute Nodes.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study.
Proceedings of the 2004 Design, 2004

2003
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.
Proceedings of the 2003 Design, 2003

2002
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2001


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