Hans-Jörg Pfleiderer

Affiliations:
  • University of Ulm, Germany


According to our database1, Hans-Jörg Pfleiderer authored at least 38 papers between 1979 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1990, "For contributions to CCD circuit and filter design.".

Timeline

Legend:

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In proceedings 
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Links

Online presence:

On csauthors.net:

Bibliography

2009
Numerically controlled oscillators using linear approximation.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Fully programmable layered LDPC decoder architecture.
Proceedings of the 17th European Signal Processing Conference, 2009

2008
EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs.
Proceedings of the FPL 2008, 2008

FPGA implementation of a flexible decoder for long LDPC codes.
Proceedings of the FPL 2008, 2008

Configurable Blocks for Multi-precision Multiplication.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Self-calibrating microphone arrays for speech signal acquisition: A systematic approach.
Signal Process., 2006

Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Regular Routing Architecture for a LUT-based MPGA.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

LUT-based MPGAs for fast turnaround time conversion flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power estimation of a LUT-based MPGA.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
Comprehensive pharmacokinetic model of insulin Glargine and other insulin formulations.
IEEE Trans. Biomed. Eng., 2005

3D Chip Stack Technology Using Through-Chip Interconnects.
IEEE Des. Test Comput., 2005

Vertical Sorting Techniques Accelerating Associative Accesses based Information Retrieval Systems.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

An Interactive Systemc Course Featuring Real-Time Online Compiling and Analysis.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

Efficient Hardware Search Engine for Associative Content Retrieval of Long Queries in Huge Multimedia Databases.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

2004
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures.
Proceedings of the Integrated Circuit and System Design, 2004

A scalable compact architecture for the computation of integer binary logarithms through linear approximation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays.
Proceedings of the Field Programmable Logic and Application, 2004

A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data.
Proceedings of the Field Programmable Logic and Application, 2004

High Performance Associative Coprocessor Architecture for Advanced Database Searching.
Proceedings of the IASTED International Conference on Databases and Applications, 2004

2003
Modelling the glucose metabolism with backpropagation through time trained Elman nets.
Proceedings of the NNSP 2003, 2003

A driver load model for capacitive coupled on-chip interconnect buses.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2002
Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach.
Discret. Event Dyn. Syst., 2002

Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Petri Net Based Design and Implementation Methodology for Discrete Event Control Systems.
Proceedings of the Application and Theory of Petri Nets 2001, 2001

1999
Self-timed MESFET gallium arsenide circuit techniques for a direct digital frequency synthesiser.
Proceedings of the ISSPA '99. Proceedings of the Fifth International Symposium on Signal Processing and its Applications, 1999

Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI.
Proceedings of the VLSI: Systems on a Chip, 1999

1996
Large bandwidth BiCMOS operational amplifiers for SC video applications.
IEEE J. Solid State Circuits, 1996

1995
An ECL to CMOS level converter with complementary bipolar output stage.
IEEE J. Solid State Circuits, July, 1995

Symbolic pole/zero calculation using SANTAFE.
IEEE J. Solid State Circuits, July, 1995

1985
VLSI - Auswirkungen auf konventionelle Rechnerstrukturen.
Inform. Spektrum, 1985

1983
A function-independent self-test for large programmable logic arrays.
Integr., 1983

1979
Antialiasing Filter with an Improved S/N Ratio.
IEEE Trans. Commun., 1979


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