Gerald S. Leatherman

According to our database, Gerald S. Leatherman authored at least 4 papers between 2015 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

A Reliability Overview of Intel's 10+ Logic Technology.

Rohit Grover, Tony Acosta, C. AnDyke, Emre Armagan, C. Auth, Sunny Chugh, K. Downes, M. Hattendorf, N. Jack, S. Joshi, R. Kasim, Gerald S. Leatherman, S.-H. Lee, C.-Y. Lin, A. Madhavan, H. Mao, A. Lowrie, G. Martin, G. McPherson, Pinakpani Nayak, A. Neale, D. Nminibapiel, Benjamin Orr, James Palmer, C. M. Pelto, S. S. Poon, I. Post, Tanmoy Pramanik, Anisur Rahman, Stephen Ramey, N. Seifert, K. Sethi, Anthony Schmitz, H. Wu, A. Yeoh

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2018

Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG.

Anisur Rahman, Javier Dacuña, Pinakpani Nayak, Gerald S. Leatherman, Stephen Ramey

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology.

F. Griggio, James Palmer, F. Pan, N. Toledo, Anthony Schmitz, Ilan Tsameret, R. Kasim, Gerald S. Leatherman, Jeffery Hicks, A. Madhavan, J. Shin, J. Steigerwald, A. Yeoh, C. Auth

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2015

Package induced stress impact on transistor performance for ultra-thin SoC.

Md. Enamul Kabir, Dave Young, Bahattin Kilic, Ioan Sauciuc, Carl Sapp, Gerald S. Leatherman

Proceedings of the IEEE International Reliability Physics Symposium, 2015