Gerd Spalink

According to our database1, Gerd Spalink authored at least 4 papers between 2022 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion.
IEEE J. Solid State Circuits, September, 2023

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.
IEEE J. Solid State Circuits, 2023

2022
A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022


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