Peng Chen

According to our database, Peng Chen authored at least 16 papers between 2015 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.

Xi Meng, Haoran Li, Peng Chen, Jun Yin, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.

Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie

IEEE J. Solid State Circuits, 2023

2022

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS.

Peng Chen, Jun Yin, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS.

Peng Chen, Xi Meng, Jun Yin, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.

Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS.

Feifei Zhang, Peng Chen, Jeffrey S. Walling, Anding Zhu, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS.

Suoping Hu, Peng Chen, Philip Quinlan, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Type-II Phase-Tracking Receiver.

Suoping Hu, Jianglin Du, Peng Chen, Hieu Minh Nguyen, Philip Quinlan, Teerachot Siriburanon, Robert Bogdan Staszewski

IEEE J. Solid State Circuits, 2021

A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range.

Peng Chen, Feifei Zhang, Suoping Hu, Robert Bogdan Staszewski

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2019

A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications.

Zhirui Zong, Peng Chen, Robert Bogdan Staszewski

IEEE J. Solid State Circuits, 2019

A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS.

Peng Chen, Feifei Zhang, Zhirui Zong, Suoping Hu, Teerachot Siriburanon, Robert Bogdan Staszewski

IEEE J. Solid State Circuits, 2019

2018

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop.

Peng Chen, Xiongchuan Huang, Yue Chen, Lianbo Wu, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS.

Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Exponential extended flash time-to-digital converter.

Peng Chen, Robert Bogdan Staszewski

Proceedings of the Second International Conference on Event-based Control, 2016

2015

Fractional spur suppression in all-digital phase-locked loops.

Peng Chen, Xiongchuan Huang, Robert Bogdan Staszewski

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs.

Peng Chen, Xiongchuan Huang, Yao-Hong Liu, Ming Ding, Cui Zhou, Ao Ba, Kathleen Philips, Harmke de Groot, Robert Bogdan Staszewski

Proceedings of the ESSCIRC Conference 2015, 2015