Didier Belot

According to our database1, Didier Belot authored at least 66 papers between 1995 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Toward 6G: From New Hardware Design to Wireless Semantic and Goal-Oriented Communication Paradigms.
CoRR, 2021

Convergent Communication, Sensing and Localization in 6G Systems: An Overview of Technologies, Opportunities and Challenges.
IEEE Access, 2021

2020
6G White Paper on Localization and Sensing.
CoRR, 2020

Technology Roadmap for Beyond 5G Wireless Connectivity in D-band.
Proceedings of the 2nd 6G Wireless Summit, 2020

2015
Design of 28 nm CMOS integrated transformers for a 60 GHz power amplifier.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A novel tunable impedance transmission line for mm-waves applications.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2.10 A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Design of a wideband 1.5GHz to 3GHz class EF2 power amplifier.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

The P/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A mmW low power VCO with high tuning range in 28nm FDSOI CMOS technology.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

80 GHz co-designed LNA and antenna for automotive radar.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

2013
Codesign of a PA-Antenna Block in Silicon Technology for 80-GHz Radar Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Fully integrated Doherty power amplifier electromagnetically optimized in CMOS 65nm with constant PAE in backoff.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Study and analysis of a new implementation of a mixed-signal cartesian feedback for a low power zero-IF WCDMA transmitter.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A 2.535 GHz fully integrated Doherty power amplifier in CMOS 65nm with constant PAE in backoff.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Optimization of 65nm CMOS passive devices to design a 16 dBm-Psat 60 GHz power amplifier.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

F1: Advanced RF transceiver design techniques.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Full Software Radio transceivers.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
On the electrical properties of slotted metallic planes in CMOS processes for RF and millimeter-wave applications.
Microelectron. J., 2012

A 65nm CMOS 60 GHz class F-E power amplifier for WPAN applications.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A 60GHz class F-E power VCO with vector-modulator feedback in 65nm CMOS technology.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications.
IEEE J. Solid State Circuits, 2011

A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Gb/s+ portable wireless communications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A low-power 2 GHz discrete time weighting system dedicated to Sampled Analog Signal Processing.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
The Experimental Demonstration of a SASP-Based Full Software Radio Receiver.
IEEE J. Solid State Circuits, 2010

A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Reconfigurable RF and data converters.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 65nm CMOS fully integrated 31.5 dBm triple SFDS Power Amplifier dedicated to W-CDMA application.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

On the receiver system feasibility for mobile DVB - S applications in the Ku - band (10.7 - 12.75 GHz).
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Low power and high gain double-balanced mixer dedicated to 77 GHz automotive radar applications.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A comparison between grounded and floating shield inductors for mmW VCOs.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era.
Proc. IEEE, 2009

A novel delta sigma built-in-current-sensor as a signal strength indicator for RF transceiver reconfiguration.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

CMOS SFFDS PA with Coupled Transformer for High Power RF Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Millimeter-Waves building block design methodology in BiCMOS technology.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Shielding structures for millimeter-wave integrated transformers.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
A Disruptive Receiver Architecture Dedicated to Software-Defined Radio.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Design of Class-E power VCO in 65nm CMOS technology: Application to RF transmitter architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 65 nm CMOS - Stacked Folded Fully Differential (SFFD) PA structure for W-CDMA application.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Switchable-Order G<sub>m</sub>-C Baseband Filter With Wide Digital Tuning for Configurable Radio Receivers.
IEEE J. Solid State Circuits, 2007

A 2GHz 0.25μm SiGe BiCMOS Oscillator with Flip-Chip Mounted BAW Resonator.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Novel LNA Topology with Transformer-based Input Integrated Matching and its 60-GHz Millimeter-wave CMOS 65-nm Design.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
A transmitter architecture for nonconstant envelope modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Phase locked loop robustness improvement using non integer order loop filter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Improved Isolation W-CDMA Ladder BAW-SMR Filter.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design and Implementation of BiFET LNAs for W-CDMA / IEEE 802.11a Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Digital Radio Front-End for High Data Rate Impulse UWB System.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Reconfiguration of Bulk Acoustic Wave Filters: Application to WLAN 802.11b/g (2.40-2.48 GHz).
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Analysis of the intermodulation distortion and nonlinearity of common-base SiGeC HBTs.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Concurrent Dual-Band Low Noise Amplifier for 802.11a/g WLAN applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design of a SiGe Reconfigurable Power Amplifier for RF Applications: Device and Multi-standard Considerations.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A 1 V 270 My-W 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler.
J. Low Power Electron., 2005

Design of a fully-integrated BiCMOS/FBAR reconfigurable RF receiver front-end.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Dual-standard BiCMOS LNA for DCS1800/W-CDMA applications.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

20 dBm CMOS class AB power amplifier design for low cost 2 GHz-2.45 GHz consumer applications in a 0.13µm technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fully-integrated low-consumption BiFET low-noise amplifier for WCDMA applications.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A fully integrated differential 5-6GHz LNA with on-chip balun for WLAN applications.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Dual-mode RF receiver front-end using a 0.25-µm 60-GHz f<sub>T</sub>SiGe: C BiCMOS7RF technology.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2002
Substrate Parasitic Extraction for RF Integrated Circuits.
Proceedings of the 2002 Design, 2002

1995
A 622/155 mbps ATM line terminator mono-chip.
Proceedings of the 1995 European Design and Test Conference, 1995


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