Cecilia Metra

J. Electron. Test., 2013

Novel approach to reduce power droop during scan-based logic BIST.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

New Design for Testability Approach for Clock Fault Testing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Faults affecting the control blocks of PV arrays and techniques for their concurrent detection.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.

[BibT_eX]

[DOI]

Alessandro Paccagnella

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems.

[BibT_eX]

[DOI]

Rajesh Galivanche

IEEE Trans. Computers, 2011

Impact of Aging Phenomena on Soft Error Susceptibility.

[BibT_eX]

[DOI]

Alessandro Paccagnella

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Error correcting code analysis for cache memory high reliability and performance.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

High-Performance Robust Latches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Secure communication protocol for wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Transient Fault and Soft Error On-die Monitoring Scheme.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

Novel low-cost aging sensor.

[BibT_eX]

[DOI]

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

Accurate Linear Model for SET Critical Charge Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Testing Resistive Opens and Bridging Faults Through Pulse Propagation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates.

[BibT_eX]

[DOI]

J. Electron. Test., 2009

Novel High Speed Robust Latch.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Power Consumption of Fault Tolerant Busses.

[BibT_eX]

[DOI]

André K. Nieuwland

Steven V. E. S. van Dijk

Richard P. Kleihorst

IEEE Trans. Very Large Scale Integr. Syst., 2008

Checkers' No-Harm Alarms and Design Approaches to Tolerate Them.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Simultaneous Switching Noise: The Relation between Bus Layout and Coding.

[BibT_eX]

[DOI]

André K. Nieuwland

IEEE Des. Test Comput., 2008

Risks for Signal Integrity in System in Package and Possible Remedies.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Latch Susceptibility to Transient Faults and New Hardening Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Guest Editors' Introduction: The State of the Art in Nanoscale CAD.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Novel Approach to Clock Fault Testing for High Performance Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Novel compensation scheme for local clocks of high performance microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Configurable Error Control Scheme for NoC Signal Integrity.

[BibT_eX]

[DOI]

Paolo Angelini

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Testing Reversible One-Dimensional QCA Arrays for Multiple Faults.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Interactive presentation: Pulse propagation for the detection of small delay defects.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC).

[BibT_eX]

[DOI]

Jien-Chung Lo

IEEE Trans. Computers, 2006

Checker No-Harm Alarm Robustness.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Testing Reversible 1D Arrays for Molecular QCA.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Can Clock Faults be Detected Through Functional Test?

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Analysis of the impact of bus implemented EDCs on on-chip SSN.

[BibT_eX]

[DOI]

Carlo Steiner

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Novel on-chip circuit for jitter testing in high-speed PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2005

Low Cost and High Speed Embedded Two-Rail Code Checker.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Self-Checking Voter for High Speed TMR Systems.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

New ECC for Crosstalk Impact Minimization.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

Exploiting ECC Redundancy to Minimize Crosstalk Impact.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

Low Cost Scheme for On-Line Clock Skew Compensation.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Coding Techniques for Low Switching Noise in Fault Tolerant Busses.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.

[BibT_eX]

[DOI]

Yuvraj Singh Dhillon

Abdulkadir Utku Diril

Abhijit Chatterjee

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Multiple Transient Faults in Logic: An Issue for Next Generation ICs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

The Other Side of the Timing Equation: a Result of Clock Faults.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

TMR voting in the presence of crosstalk faults at the voter inputs.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2004

Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Model for Transient Fault Susceptibility of Combinational Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates.

[BibT_eX]

[DOI]

André Ivanov

IEEE Des. Test Comput., 2004

Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Hardware Reconfiguration Scheme for High Availability Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

New High Speed CMOS Self-Checking Voter.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Fast and Low-Cost Clock Deskew Buffer.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Are Our Design for Testability Features Fault Secure?

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Fault secureness need for next generation high performance microprocessor design for testability structures.

[BibT_eX]

[DOI]

Proceedings of the First Conference on Computing Frontiers, 2004

2003

Concurrent detection of power supply noise.

[BibT_eX]

[DOI]

Luca Schiano

IEEE Trans. Reliab., 2003

Self-checking design, implementation, and measurement of a controller for track-side railway systems.

[BibT_eX]

[DOI]

Luca Schiano

Diego Marino

IEEE Trans. Instrum. Meas., 2003

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults.

[BibT_eX]

[DOI]

Microelectron. J., 2003

Error Correcting Strategy for High Speed and High Density Reliable Flash Memories.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Guest Editorial.

[BibT_eX]

[DOI]

Matteo Sonza Reorda

J. Electron. Test., 2003

Novel Transient Fault Hardened Static Latch.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Crosstalk Effect Minimization for Encoded Busses.

[BibT_eX]

[DOI]

L. Di Silvio

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Power Consumption of Fault Tolerant Codes: the Active Elements.

[BibT_eX]

[DOI]

Steven V. E. S. van Dijk

Richard P. Kleihorst

André K. Nieuwland

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A Model for Transient Fault Propagation in Combinatorial Logic.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Error Correcting Codes for Crosstalk Effect Minimization.

[BibT_eX]

[DOI]

S. Cavallotti

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Automatic Modification of Sequential Circuits for Self-Checking Implementation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

High Speed and Highly Testable Parallel Two-Rail Code Checker.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Guest Editorial.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

On-Chip Clock Faults' Detector.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Online Testing Approach for Very Deep-Submicron ICs.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems.

[BibT_eX]

[DOI]

Luca Schiano

Diego Marino

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Coding Scheme for Low Energy Consumption Fault-Tolerant Bus.

[BibT_eX]

[DOI]

Steven V. E. S. van Dijk

Richard P. Kleihorst

A. H. Nieuwland

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits.

[BibT_eX]

[DOI]

Giuseppe Marrale

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Self-Checking Scheme for the On-Line Testing of Power Supply Noise.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems.

[BibT_eX]

IEEE Des. Test Comput., 2001

On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems.

[BibT_eX]

[DOI]

Andrea Pagano

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Novel Fault-Tolerant Adder Design for FPGA-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Optimization of error detecting codes for the detection of crosstalk originated errors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits.

[BibT_eX]

[DOI]

VLSI Design, 2000

Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Intermediacy Prediction for High Speed Berger Code Checkers.

[BibT_eX]

[DOI]

Jien-Chung Lo

J. Electron. Test., 2000

Bridging Faults in Pipelined Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

Self-checking scheme for very fast clocks' skew correction.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems.

[BibT_eX]

[DOI]

Sergio D'Angelo

Giacomo R. Sechi

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

On the Design of Self-Checking Functional Units Based on Shannon Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Concurrent Checking of Clock Signal Correctness.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1998

On-line detection of logic errors due to crosstalk, delay, and transient faults.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Novel Technique for Testing FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Highly Testable and Compact 1-out-of-n Code Checker with Single Output.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Highly testable and compact single output comparator.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On-Line Testing Scheme for Clock's Faults.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Compact and low power on-line self-testing voting scheme.

[BibT_eX]

[DOI]

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Fast and area-time efficient Berger code checkers.

[BibT_eX]

[DOI]

Yu-Yau Guo

Jien-Chung Lo

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Low-level error recovery mechanism for self-checking sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Testing scheme for IC's clocks.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Sensing circuit for on-line detection of delay faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1996

Embedded two-rail checkers with on-line testing ability.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Tree Checkers for Applications with Low Power-Delay Requirements.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Compact and Highly Testable Error Indicator for Self-Checking Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.

[BibT_eX]

[DOI]

J. Electron. Test., 1995

Novel Berger code checker.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994

Highly Testable and Compact 1-out-of-n CMOS Checkers.

[BibT_eX]

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

CMOS Self Checking Circuits with Faulty Sequential Functional Block.

[BibT_eX]