Giovanni Marucci

According to our database1, Giovanni Marucci authored at least 9 papers between 2013 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
Techniques for high-efficiency digital frequency synthesis.
PhD thesis, 2015

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop.
IEEE J. Solid State Circuits, 2015

2014
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A spur cancellation technique for MDLL-based frequency synthesizers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An efficient method to compute phase-noise in injection-locked frequency dividers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Minimum-jitter design of bang-bang PLLs in the presence of 1/f<sup>2</sup> and 1/f<sup>3</sup> DCO noise.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013


  Loading...