Go Matsukawa

According to our database, Go Matsukawa authored at least 10 papers between 2014 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations.

Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Go Matsukawa, Toshio Goto, Motoshi Kojima

IEEE J. Sel. Top. Signal Process., 2020

2018

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668].

Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto

IEICE Electron. Express, 2018

2017

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video.

Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto

IEICE Electron. Express, 2017

FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature.

Yuri Nishizumi, Go Matsukawa, Koichi Kajihara, Taisuke Kodama, Shintaro Izumi, Hiroshi Kawaguchi, Chikako Nakanishi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

2016

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path.

Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

An soft error propagation analysis considering logical masking effect on re-convergent path.

Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.

Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2015

An accurate soft error propagation analysis technique considering temporal masking disablement.

Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path.

Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM.

Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the ARCS 2014, 2014