Gregory Malecha

Orcid: 0000-0003-3952-0807

Affiliations:
  • BedRock Systems, Menlo Park, USA
  • Harvard University, Cambridge, USA (former)


According to our database1, Gregory Malecha authored at least 23 papers between 2008 and 2022.

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Timeline

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Bibliography

2022
Developing With Formal Methods at BedRock Systems, Inc.
IEEE Secur. Priv., 2022

2021
Formal Methods for the Informal Engineer: Workshop Recommendations.
CoRR, 2021

2020
Interaction trees: representing recursive and impure programs in Coq.
Proc. ACM Program. Lang., 2020

The MetaCoq Project.
J. Autom. Reason., 2020

2019
Interaction Trees: Representing Recursive and Impure Programs in Coq (Work In Progress).
CoRR, 2019

2016
Extensible and Efficient Automation Through Reflective Tactics.
Proceedings of the Programming Languages and Systems, 2016

Modular deductive verification of sampled-data systems.
Proceedings of the 2016 International Conference on Embedded Software, 2016

Towards foundational verification of cyber-physical systems.
Proceedings of the 2016 Science of Security for Cyber-Physical Systems Workshop, 2016

2015
Automated software winnowing.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Towards verification of hybrid systems in a foundational proof assistant.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Using dependent types and tactics to enable semantic optimization of language-integrated queries.
Proceedings of the 15th Symposium on Database Programming Languages, 2015

2014
Compositional Computational Reflection.
Proceedings of the Interactive Theorem Proving - 5th International Conference, 2014

2013
MirrorShard: Proof by Computational Reflection with Verified Hints
CoRR, 2013

2012
Hardware Support for Safety Interlocks and Introspection.
Proceedings of the Sixth IEEE International Conference on Self-Adaptive and Self-Organizing Systems Workshops, 2012

2011
Static consistency checking for Verilog wire interconnects - Using dependent types to check the sanity of Verilog descriptions.
High. Order Symb. Comput., 2011

Trace-based verification of imperative programs with I/O.
J. Symb. Comput., 2011

Preliminary design of the SAFE platform.
Proceedings of the 6th Workshop on Programming Languages and Operating Systems, 2011

2010
Synthesizable High Level Hardware Descriptions.
New Gener. Comput., 2010

Toward a verified relational database management system.
Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2010

A more precise security type system for dynamic security tests.
Proceedings of the 2010 Workshop on Programming Languages and Analysis for Security, 2010

Mechanized Verification with Sharing.
Proceedings of the Theoretical Aspects of Computing, 2010

2009
Effective interactive proofs for higher-order imperative programs.
Proceedings of the Proceeding of the 14th ACM SIGPLAN international conference on Functional programming, 2009

2008
Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability.
Proceedings of the 2008 ACM SIGPLAN Symposium on Partial Evaluation and Semantics-based Program Manipulation, 2008


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