Udit Dhawan

According to our database, Udit Dhawan authored at least 8 papers between 2011 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

MARS: Memory Aware Reordered Source.

Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang

CoRR, 2018

2015

Area-Efficient Near-Associative Memories on FPGAs.

Udit Dhawan, André DeHon

ACM Trans. Reconfigurable Technol. Syst., 2015

Architectural Support for Software-Defined Metadata Processing.

Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs.

Sharad Sinha, Udit Dhawan, Thambipillai Srikanthan

J. Circuits Syst. Comput., 2014

PUMP: a programmable unit for metadata processing.

Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon

Proceedings of the HASP 2014, 2014

2013

Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security.

Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight Jr., André DeHon

Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

2012

Hardware Support for Safety Interlocks and Introspection.

Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, André DeHon, Gregory Malecha, Greg Morrisett, Thomas F. Knight Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David K. Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan

Proceedings of the Sixth IEEE International Conference on Self-Adaptive and Self-Organizing Systems Workshops, 2012

2011

A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis.

Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011