André DeHon

Orcid: 0000-0001-9177-7699

Affiliations:
  • University of Pennsylvania, Philadelphia, USA


According to our database1, André DeHon authored at least 129 papers between 1994 and 2023.

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Bibliography

2023
Asymmetry in Butterfly Fat Tree FPGA NoC.
Proceedings of the International Conference on Field Programmable Technology, 2023

2022
SCALPEL: Exploring the Limits of Tag-enforced Compartmentalization.
ACM J. Emerg. Technol. Comput. Syst., 2022

Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration.
Proceedings of the International Conference on Field-Programmable Technology, 2022

HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems.
IEEE Trans. Computers, 2021

Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation.
CoRR, 2021

μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts.
Proceedings of the RAID '21: 24th International Symposium on Research in Attacks, 2021

Flightplan: Dataplane Disaggregation and Placement for P4 Programs.
Proceedings of the 18th USENIX Symposium on Networked Systems Design and Implementation, 2021

HLS-Compatible, Embedded-Processor Stream Links.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction.
Proceedings of the CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15, 2021

2020
Introduction to Special Section on FCCM 2019.
ACM Trans. Reconfigurable Technol. Syst., 2020

Mir: Automated Quantifiable Privilege Reduction Against Dynamic Library Compromise in JavaScript.
CoRR, 2020

Fast Linking of Separately-Compiled FPGA Blocks without a NoC.
Proceedings of the International Conference on Field-Programmable Technology, 2020

DeepMatch: practical deep packet inspection in the data plane using network processors.
Proceedings of the CoNEXT '20: The 16th International Conference on emerging Networking EXperiments and Technologies, 2020

2019
Ignis: scaling distribution-oblivious systems with light-touch distribution.
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Pipelined Parallel Finite Automata Evaluation.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP).
ACM Trans. Reconfigurable Technol. Syst., 2018

Protecting the Stack with Metadata Policies and Tagged Hardware.
Proceedings of the 2018 IEEE Symposium on Security and Privacy, 2018

In-network computing to the rescue of faulty links.
Proceedings of the 2018 Morning Workshop on In-Network Computing, 2018

BreakApp: Automated, Flexible Application Compartmentalization.
Proceedings of the 25th Annual Network and Distributed System Security Symposium, 2018

Case for Fast FPGA Compilation Using Partial Reconfiguration.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Self-Adaptive Timing Repair.
IEEE Des. Test, 2017

Towards Fine-grained, Automated Application Compartmentalization.
Proceedings of the 9th Workshop on Programming Languages and Operating Systems, 2017

Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
Impact of Parallelism and Memory Architecture on FPGA Communication Energy.
ACM Trans. Reconfigurable Technol. Syst., 2016

Introduction to Special Issue on Reconfigurable Components with Source Code.
ACM Trans. Reconfigurable Technol. Syst., 2016

Accurate Parallel Floating-Point Accumulation.
IEEE Trans. Computers, 2016

A verified information-flow architecture.
J. Comput. Secur., 2016

PERFECT case studies demonstrating order of magnitude reduction in power consumption.
Proceedings of the 2016 IEEE High Performance Extreme Computing Conference, 2016

Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction.
ACM Trans. Reconfigurable Technol. Syst., 2015

Area-Efficient Near-Associative Memories on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2015

Reconfigurable Computing Architectures.
Proc. IEEE, 2015

Fundamental Underpinnings of Reconfigurable Computing Architectures.
Proc. IEEE, 2015

Energy minimization in the time-space continuum.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Impact of Memory Architecture on FPGA Energy Consumption.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Architectural Support for Software-Defined Metadata Processing.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
PUMP: a programmable unit for metadata processing.
Proceedings of the HASP 2014, 2014

RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Energy Reduction through Differential Reliability and Lightweight Checking.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Exploiting partially defective LUTs: Why you don't need perfect fabrication.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Location, location, location: the role of spatial locality in asymptotic energy minimization.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security.
Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

2012
${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Hardware Support for Safety Interlocks and Introspection.
Proceedings of the Sixth IEEE International Conference on Self-Adaptive and Self-Organizing Systems Workshops, 2012

FPGA optimized packet-switched NoC using split and merge primitives.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Limit study of energy & delay benefits of component-specific routing.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
Choose-your-own-adventure routing: Lightweight load-time defect avoidance.
ACM Trans. Reconfigurable Technol. Syst., 2011

Spatial hardware implementation for sparse graph algorithms in GraphStep.
ACM Trans. Auton. Adapt. Syst., 2011

An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads.
Int. J. Reconfigurable Comput., 2011

Crystals and Snowflakes: Building Computation from Nanowire Crossbars.
Computer, 2011

Preliminary design of the SAFE platform.
Proceedings of the 6th Workshop on Programming Languages and Operating Systems, 2011

VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Variation and Aging Tolerance in FPGAs.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

Low-Power Techniques for FPGAs.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

Vision for cross-layer optimization to address the dual challenges of energy and reliability.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Fault Secure Encoder and Decoder for NanoMemory Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Pipelining Saturated Accumulation.
IEEE Trans. Computers, 2009

Inversion schemes for sublithographic programmable logic arrays.
IET Comput. Digit. Tech., 2009

VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

CMOS vs Nano: comrades or rivals?
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Accelerating SPICE Model-Evaluation using FPGAs.
Proceedings of the FCCM 2009, 2009

2008
Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2008

2007
Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Introduction to the Special Section on Nano Systems and Computing.
IEEE Trans. Computers, 2007

Fault tolerant nano-memory with fault secure encoder and decoder.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Architecture approaching the atomic scale.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Fault Secure Encoder and Decoder for Memory Applications.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation.
Proceedings of the Fair Division, 24.06. - 29.06.2007, 2007

06361 Executive Report -- Computing Media Languages for Space-Oriented Computation.
Proceedings of the Fair Division, 24.06. - 29.06.2007, 2007

Optimistic Parallelization of Floating-Point Accumulation.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2006
Stream computations organized for reconfigurable execution.
Microprocess. Microsystems, 2006

Stochastic spatial routing for reconfigurable networks.
Microprocess. Microsystems, 2006

Radial addressing of nanowires.
ACM J. Emerg. Technol. Comput. Syst., 2006

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

3D Nanowire-Based Programmable Logic.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Tutorial 1: Emerging Technologies for VLSI Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Packet Switched vs. Time Multiplexed FPGA Overlay Networks.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

GraphStep: A System Architecture for Sparse-Graph Algorithms.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

SAT-based optimal hypergraph partitioning with replication.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Nanowire-based programmable architectures.
ACM J. Emerg. Technol. Comput. Syst., 2005

Seven Strategies for Tolerating Highly Defective Fabrication.
IEEE Des. Test Comput., 2005

Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Floating-point sparse matrix-vector multiply for FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Design of programmable interconnect for sublithographic programmable logic arrays.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Design of FPGA interconnect for multilevel metallization.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Unifying mesh- and tree-based programmable interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A greedy algorithm for tolerating defective crosspoints in nanoPLA design.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Nanowire-based sublithographic programmable logic arrays.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

What is the right model for programming and using modern FPGAs?
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Design Patterns for Reconfigurable Computing.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Hardware-assisted simulated annealing with application for fast FPGA placement.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Design of FPGA interconnect for multilevel metalization.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Stochastic, spatial routing for hypergraphs, trees, and meshes.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Very Large Scale Spatial Computing.
Proceedings of the Unconventional Models of Computation, Third International Conference, 2002

Molecular electronics: devices, systems and tools for gigagate, gigabit chips.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Hardware-Assisted Fast Routing.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Rent's rule based switching requirements.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

2000
The Density Advantage of Configurable Computing.
Computer, 2000

Compact, multilayer layout for butterfly fat-tree.
Proceedings of the Twelfth annual ACM Symposium on Parallel Algorithms and Architectures, 2000

Stream Computations Organized for Reconfigurable Execution (SCORE).
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization).
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Reconfigurable Computing: What, Why, and Implications for Design Automation.
Proceedings of the 36th Conference on Design Automation, 1999

1998
High Performance, Point-to-Point, Transmission Line Signaling.
VLSI Design, 1998

Fast Module Mapping and Placement for Datapaths in FPGAs.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Object Oriented Circuit-Generators in Java.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Seeking Solutions in Configurable Computing.
Computer, 1997

Directions in General-Purpose Computing Architectures.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

1996
Reconfigurable architectures for general-purpose computing.
PhD thesis, 1996

DPGA Utilization and Application.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Entropy, Counting, and Programmable Interconnect.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1994
Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks.
Proceedings of the Parallel Computer Routing and Communication, 1994

In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994


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