Guan-Sing Chen

According to our database, Guan-Sing Chen authored at least 3 papers between 2014 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology.

Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee

IEEE J. Solid State Circuits, 2015

2014

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS.

Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology.

Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014