Jri Lee

According to our database, Jri Lee authored at least 45 papers between 2003 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS.

Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015

A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology.

Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Yu-Lun Chen, Jri Lee

IEEE J. Solid State Circuits, 2015

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies.

Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng

IEEE J. Solid State Circuits, 2015

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology.

Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee

IEEE J. Solid State Circuits, 2015

56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS.

Jri Lee, Ping-Chuan Chiang, Chih-Chi Weng

Proceedings of the Symposium on VLSI Circuits, 2015

CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS.

Li-Yang Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

A 94GHz duobinary keying wireless transceiver in 65nm CMOS.

Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee

Proceedings of the Symposium on VLSI Circuits, 2014

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS.

Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology.

Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

100Gb/s ethernet chipsets in 65nm CMOS technology.

Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS.

Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

IEEE J. Solid State Circuits, 2012

2011

W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology.

Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee

IEEE J. Solid State Circuits, 2011

Tutorial: "Design of high-speed wireline transceivers".

Jri Lee

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS.

Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 40Gb/s TX and RX chip set in 65nm CMOS.

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet.

Ke-Chung Wu, Jri Lee

IEEE J. Solid State Circuits, 2010

A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology.

Huaide Wang, Jri Lee

IEEE J. Solid State Circuits, 2010

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology.

Jri Lee, Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang

IEEE J. Solid State Circuits, 2010

A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly.

Jri Lee, Yentso Chen, Yenlin Huang

IEEE J. Solid State Circuits, 2010

A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications.

Ke-Chung Wu, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A fully integrated 77GHz FMCW radar system in 65nm CMOS.

Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition.

Jri Lee, Ke-Chung Wu

IEEE J. Solid State Circuits, 2009

Study of Subharmonically Injection-Locked PLLs.

Jri Lee, Huaide Wang

IEEE J. Solid State Circuits, 2009

Subharmonically injection-locked PLLs for ultra-low-noise clock generation.

Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition.

Jri Lee, Ke-Chung Wu

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly.

Jri Lee, Yenlin Huang, Yentso Chen, Hsinchia Lu, Chiajung Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.

Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee

IEEE J. Solid State Circuits, 2008

A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology.

Jri Lee, Mingchung Liu, Huaide Wang

IEEE J. Solid State Circuits, 2008

A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique.

Jri Lee, Mingchung Liu

IEEE J. Solid State Circuits, 2008

Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data.

Jri Lee, Ming-Shuan Chen, Huaide Wang

IEEE J. Solid State Circuits, 2008

A 20Gb/s Duobinary Transceiver in 90nm CMOS.

Jri Lee, Ming-Shuan Chen, Huaide Wang

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Gigabit CDRs Equalizers.

John T. Stonick, Jri Lee

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 20Gb/s Broadband Transmitter with Auto-Configuration Technique.

Jri Lee, Huaide Wang

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique.

Jri Lee, Mingchung Liu

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 75-GHz PLL in 90-nm CMOS Technology.

Jri Lee

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology.

Jri Lee

IEEE J. Solid State Circuits, 2006

High-speed circuit designs for transmitters in broadband data links.

Jri Lee

IEEE J. Solid State Circuits, 2006

A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology.

Jri Lee

IEEE J. Solid State Circuits, 2006

A 20Gb/s Adaptive Equalizer in 0.13µm CMOS Technology.

Jri Lee

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology".

Jri Lee, Behzad Razavi

IEEE J. Solid State Circuits, 2005

2004

A 40-GHz frequency divider in 0.18-μm CMOS technology.

Jri Lee, Behzad Razavi

IEEE J. Solid State Circuits, 2004

Analysis and modeling of bang-bang clock and data recovery circuits.

Jri Lee, Kenneth S. Kundert, Behzad Razavi

IEEE J. Solid State Circuits, 2004

2003

A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology.

Jri Lee, Behzad Razavi

IEEE J. Solid State Circuits, 2003

Modeling of jitter in bang-bang clock and data recovery circuits.

Jri Lee, Kenneth S. Kundert, Behzad Razavi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003