Jri Lee

According to our database1, Jri Lee authored at least 37 papers between 2006 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies.
IEEE J. Solid State Circuits, 2015

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 94GHz duobinary keying wireless transceiver in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
100Gb/s ethernet chipsets in 65nm CMOS technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2012

2011
W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2011

Tutorial: "Design of high-speed wireline transceivers".
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 40Gb/s TX and RX chip set in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet.
IEEE J. Solid State Circuits, 2010

A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2010

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2010

A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly.
IEEE J. Solid State Circuits, 2010

A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A fully integrated 77GHz FMCW radar system in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2009

Study of Subharmonically Injection-Locked PLLs.
IEEE J. Solid State Circuits, 2009

Subharmonically injection-locked PLLs for ultra-low-noise clock generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2008

A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology.
IEEE J. Solid State Circuits, 2008

A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique.
IEEE J. Solid State Circuits, 2008

Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data.
IEEE J. Solid State Circuits, 2008

A 20Gb/s Duobinary Transceiver in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Gigabit CDRs Equalizers.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 20Gb/s Broadband Transmitter with Auto-Configuration Technique.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 75-GHz PLL in 90-nm CMOS Technology.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 20Gb/s Adaptive Equalizer in 0.13µm CMOS Technology.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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