Ángel López García-Arias
Orcid: 0000-0002-3206-1479
According to our database1,
Ángel López García-Arias
authored at least 11 papers
between 2018 and 2024.
Collaborative distances:
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Bibliography
2024
CoRR, 2024
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access, 2024
2023
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the International Conference on Machine Learning, 2022
2021
Proceedings of the 32nd British Machine Vision Conference 2021, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018