Seh-Woong Jeong

According to our database1, Seh-Woong Jeong authored at least 19 papers between 1990 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem.
Proceedings of the Design, Automation and Test in Europe, 2009

2007
A 40-to-800MHz Locking Multi-Phase DLL.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications.
IEEE J. Solid State Circuits, 2006

2003
An Intelligent Cache System with Hardware Prefetching for High Performance.
IEEE Trans. Computers, 2003

2002
A banked-promotion translation lookaside buffer system.
J. Syst. Archit., 2002

A Low Power TLB Structure for Embedded Systems.
IEEE Comput. Archit. Lett., 2002

Grouped zerotree wavelet image coding for very low bit rate.
Proceedings of the 2002 International Conference on Image Processing, 2002

2001
CalmRISC<sup>TM</sup>: a low power microcontroller with efficient coprocessor interface.
Microprocess. Microsystems, 2001

Reducing Cache Pollution of Prefetching in a Small Data Cache.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A Banked-Promotion TLB for High Performance and Low Power.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A Low-Power Cache Design for CalmRISC<sup>TM</sup>-Based Systems.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1999
CalmRISC<sup>TM</sup>: A Low Power Microcontroller with Efficient Coprocessor Interface.
Proceedings of the IEEE International Conference On Computer Design, 1999

1994
Exact calculation of synchronizing sequences based on binary decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993
Synchronizing sequences and symbolic traversal techniques in test generation.
J. Electron. Test., 1993

1992
A new algorithm for the binate covering problem and its application to the minimization of Boolean relations.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams.
Proceedings of the 29th Design Automation Conference, 1992

1991
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
ATPG Aspects of FSM Verification.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Results on the Interface between Formal Verification and ATPG.
Proceedings of the Computer-Aided Verification, 1990


  Loading...