Haikun Zhu

According to our database1, Haikun Zhu authored at least 12 papers between 2003 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2008
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Clock Skew Analysis via Vector Fitting in Frequency Domain.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Low power passive equalizer optimization using tritonic step response.
Proceedings of the 45th Design Automation Conference, 2008

Timing-power optimization for mixed-radix Ling adders by integer linear programming.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

High performance current-mode differential logic.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Passive compensation for high performance inter-chip communication.
Proceedings of the 25th International Conference on Computer Design, 2007

An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
On the construction of zero-deficiency parallel prefix circuits with minimum depth.
ACM Trans. Design Autom. Electr. Syst., 2006

2005
Constructing zero-deficiency parallel prefix adder of minimum depth.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
An Algorithmic Approach for Generic Parallel Adders.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003


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