Ernest S. Kuh

Proceedings of the 2011 International Symposium on Physical Design, 2011

2009

Design methodology of high performance on-chip global interconnect using terminated transmission-line.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

High performance on-chip differential signaling using passive compensation for global communication.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Efficient and accurate eye diagram prediction for high speed signaling.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Low Power Passive Equalizer Design for Computer Memory Links.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

Low power passive equalizer optimization using tritonic step response.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Two-Stage Newton-Raphson Method for Transistor-Level Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

An unconditional stable general operator splitting method for transistor level transient analysis.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Efficient transient simulation for transistor-level analysis.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2002

Accurate reduced RL model for frequency dependent transmission lines.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

Moment computation of lumped and distributed coupled RC trees with application to delay and crosstalk estimation.

[BibT_eX]

[DOI]

Proc. IEEE, 2001

New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Floorplan sizing by linear programming approximation.

[BibT_eX]

[DOI]

Pinghong Chen

Proceedings of the 37th Conference on Design Automation, 2000

1999

The Chebyshev expansion based passive model for distributed interconnect networks.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Coupled Noise Estimation for Distributed RC Interconnect Model.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Sequence-pair based placement method for hard/soft/pre-placed modules.

[BibT_eX]

[DOI]

Hiroshi Murata

Proceedings of the 1998 International Symposium on Physical Design, 1998

A new general connectivity model and its applications to timing-driven Steiner tree routing.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Multipoint moment matching model for multiport distributed interconnect networks.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Combining Technology Mapping With Layout.

[BibT_eX]

[DOI]

Massoud Pedram

Narasimha B. Bhat

VLSI Design, 1997

A performance-driven IC/MCM placement algorithm featuring explicit design space exploration.

[BibT_eX]

[DOI]

Henrik Esbensen

ACM Trans. Design Autom. Electr. Syst., 1997

Post global routing crosstalk synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

TIGER: an efficient timing-driven global router for gate array and standard cell layout design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits.

[BibT_eX]

[DOI]

Premal Buch

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Physical design: reminiscing and looking ahead.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Physical Design, 1997

1996

Moment models of general transmission lines with application to interconnect analysis and optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1996

Post global routing crosstalk risk estimation and reduction.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Simulation and sensitivity analysis of transmission line circuits by the characteristics method.

[BibT_eX]

[DOI]

Jun-Fa Mao

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Performance-Driven Interconnect Global Routing.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

EXPLORER: an interactive floorplanner for design space exploration.

[BibT_eX]

[DOI]

Henrik Esbensen

Proceedings of the conference on European design automation, 1996

1995

Exact moment matching model of transmission lines and application to interconnect delay estimation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1995

Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's.

[BibT_eX]

[DOI]

Akira Onozawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Techniques for fast circuit simulation applied to power estimation of CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Post routing performance optimization via multi-link insertion and non-uniform wiresizing.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Post routing performance optimization via tapered link insertion and wiresizing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

1993

Stepwise equivalent conductance circuit simulation technique.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

A new performance-driven global routing algorithm for gate array.

[BibT_eX]

Takashi Fujii

Proceedings of the VLSI 93, 1993

Circuit simulation for large interconnected IC networks.

[BibT_eX]

Proceedings of the VLSI 93, 1993

A spacing algorithm for performance enhancement and cross-talk reduction.

[BibT_eX]

[DOI]

Akira Onozawa

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Quadratic Boolean Programming for Performance-Driven System Partitioning.

[BibT_eX]

[DOI]

Minshine Shih

Proceedings of the 30th Design Automation Conference. Dallas, 1993

An Efficient Timing-Driven Global Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Performance-Driven Steiner Tree Algorithm for Global Routing.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

A New Accurate and Efficient Timing Simulator.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on VLSI Design, 1992

Transient simulation of lossy coupled transmission lines.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

Performance-Driven System Partitioning on Multi-Chip Modules.

[BibT_eX]

[DOI]

Minshine Shih

Ren-Song Tsay

Proceedings of the 29th Design Automation Conference, 1992

Power and Ground Network Topology Optimization for Cell Based VLSIs.

[BibT_eX]

[DOI]

Takashi Mitsuhashi

Proceedings of the 29th Design Automation Conference, 1992

Transient Simulation of Lossy Interconnect.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

FARM: An Efficient Feed-Through Pin Assignment Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

New Algorithms For Two- and Three-Layer Channel Routin.

[BibT_eX]

[DOI]

Deborah C. Wang

Int. J. Circuit Theory Appl., 1991

I/O Pad Assignment Based on the Circuit Structure.

[BibT_eX]

[DOI]

Massoud Pedram

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

RITUAL: Performance Driven Placement Algorithm for Small Cell ICs.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

1990

A Simulation-Based Method for Generating Tests for Sequential Circuits.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Vishwani D. Agrawal

IEEE Trans. Computers, 1990

Recent advances in VLSI layout.

[BibT_eX]

[DOI]

Tatsuo Ohtsuki

Proc. IEEE, 1990

Geometric approach to VLSI layout compaction.

[BibT_eX]

[DOI]

Xiao-Ming Xiong

Int. J. Circuit Theory Appl., 1990

Floorplanning with Pin Assignment.

[BibT_eX]

[DOI]

Massoud Pedram

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A Fast Algorithm for Performance-Driven Placement.

[BibT_eX]

[DOI]

Michael A. B. Jackson

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

MOLE: a sea-of-gates detailed router.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference, 1990

Delay and Area Optimization in Standard-Cell Design.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Clock Routing for High-Performance ICs.

[BibT_eX]

[DOI]

Michael A. B. Jackson

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Performance-driven Placement of Cell Based IC's.

[BibT_eX]

[DOI]

Michael A. B. Jackson

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

PROUD: a sea-of-gates placement algorithm.

[BibT_eX]

[DOI]

Ren-Song Tsay

Chi-Ping Hsu

IEEE Des. Test, 1988

Hierarchical placement for macrocells: a 'meet in the middle' approach.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A sequential circuit test generation using threshold-value simulation.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Vishwani D. Agrawal

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

The Constrained Via Minimization Problem for PCB and VLSI Design.

[BibT_eX]

[DOI]

Xiao-Ming Xiong

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

Proud: A Fast Sea-of-Gates Placement Algorithm.

[BibT_eX]

[DOI]

Ren-Song Tsay

Chi-Ping Hsu

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout.

[BibT_eX]

[DOI]

Wayne Wei-Ming Dai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

Nutcracker: An Efficient and Intelligent Channel Spacer.

[BibT_eX]

[DOI]

Xiao-Ming Xiong

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

A Dynamic and Efficient Representation of Building-Block Layout.

[BibT_eX]

[DOI]

Wayne Wei-Ming Dai

Masao Sato

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

Glitter: A Gridless Variable-Width Channel Router.

[BibT_eX]

[DOI]

Howard H. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

1985

Routing Region Definition and Ordering Scheme for Building-Block Layout.

[BibT_eX]

[DOI]

Wayne Wei-Ming Dai

Tetsuo Asano

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

1984

An Efficient Single-Row Routing Algorithm.

[BibT_eX]

[DOI]

Tom Tsan-Kuo Tarng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

Module Placement Based on Resistive Network Optimization.

[BibT_eX]

[DOI]

Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1983

On the Layering Problem of Multilayer PWB Wiring.

[BibT_eX]

[DOI]

Shuji Tsukiyama

Isao Shirakawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

Editorial: Routing in Microelectronics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

1982

Efficient Algorithms for Channel Routing.

[BibT_eX]

[DOI]

Takeshi Yoshimura

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982

Double-row planar routing and permutation layout.

[BibT_eX]

[DOI]

Shuji Tsukiyama

Networks, 1982

1979

One-dimensional logic gate assignment and interval graphs.

[BibT_eX]

[DOI]

Tatsuo Ohtsuki

Hajimu Mori

Toshinobu Kashiwabara

Toshio Fujisawa

Proceedings of the IEEE Computer Society's Third International Computer Software and Applications Conference, 1979

Single-row routing and extensions.

[BibT_eX]

[DOI]