Rickard Ewetz

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

Integrated Decision Gradients: Compute Your Attributions Where the Model Makes Its Decision.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

STREAM: Toward READ-Based In-Memory Computing for Streaming-Based Processing for Data-Intensive Applications.

[BibT_eX]

[DOI]

Md Hafizul Islam Chowdhuryy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Understanding and Characterizing Side Channels Exploiting Phase-Change Memories.

[BibT_eX]

[DOI]

IEEE Micro, 2023

Neuro Symbolic Reasoning for Planning: Counterexample Guided Inductive Synthesis using Large Language Models and Satisfiability Solving.

[BibT_eX]

[DOI]

CoRR, 2023

Neural Stochastic Differential Equations for Robust and Explainable Analysis of Electromagnetic Unintended Radiated Emissions.

[BibT_eX]

[DOI]

CoRR, 2023

On the Robustness of AlphaFold: A COVID-19 Case Study.

[BibT_eX]

[DOI]

CoRR, 2023

Adversarial Pixel and Patch Detection Using Attribution Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Military Communications Conference, 2023

Counterexample Guided Inductive Synthesis Using Large Language Models and Satisfiability Solving.

[BibT_eX]

[DOI]

Proceedings of the IEEE Military Communications Conference, 2023

Neural SDEs for Robust and Explainable Analysis of Electromagnetic Unintended Radiated Emissions.

[BibT_eX]

[DOI]

Proceedings of the IEEE Military Communications Conference, 2023

Input-Aware Flow-Based In-Memory Computing.

[BibT_eX]

[DOI]

Suraj Singireddy

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Verification of Flow-Based Computing Systems Using Bounded Model Checking.

[BibT_eX]

[DOI]

Suraj Singireddy

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Automated Synthesis for In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Discovering the in-Memory Kernels of 3D Dot-Product Engines.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Synthesis of Clock Networks with a Mode-Reconfigurable Topology.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

XMAP: Programming Memristor Crossbars for Analog Matrix-Vector Multiplication: Toward High Precision Using Representable Matrices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A survey on the vulnerability of deep neural networks against adversarial attacks.

[BibT_eX]

[DOI]

Andy Michel

Prog. Artif. Intell., 2022

ExplainIt!: A Tool for Computing Robust Attributions of DNNs.

[BibT_eX]

[DOI]

Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022

Classifying the Ideological Orientation of User-Submitted Texts in Social Media.

[BibT_eX]

[DOI]

Kamalakkannan Ravi

Adan Ernesto Vela

Proceedings of the 21st IEEE International Conference on Machine Learning and Applications, 2022

Equivalence Checking for Flow-Based Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Logic Synthesis for Digital In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Hybrid Digital-Digital In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

PATH: evaluation of boolean logic using path-based in-memory computing.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Towards resilient analog in-memory deep learning via data layout re-organization.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

STREAM: Towards READ-based In-Memory Computing for Streaming based Data Processing.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Deep Learning Toolkit-Driven Equivalence Checking of Flow-Based Computing Systems.

[BibT_eX]

[DOI]

Suraj Singireddy

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Shaping Noise for Robust Attributions in Neural Stochastic Differential Equations.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021

Computational Restructuring: Rethinking Image Compression Using Resistive Crossbar Arrays.

[BibT_eX]

[DOI]

Md Hafizul Islam Chowdhuryy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Protein Folding Neural Networks Are Not Robust.

[BibT_eX]

[DOI]

CoRR, 2021

Seeds of SEED: R-SAW: New Side Channels Exploiting Read Asymmetry in MLC Phase Change Memories.

[BibT_eX]

[DOI]

Md Hafizul Islam Chowdhuryy

Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

LADDER: Architecting Content and Location-aware Writes for Crossbar Resistive Memories.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Automated Synthesis of Quantum Circuits Using Symbolic Abstractions and Decision Procedures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

On Smoother Attributions using Neural Stochastic Differential Equations.

[BibT_eX]

[DOI]

Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021

An OCV-Aware Clock Tree Synthesis Methodology.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Hybrid Analog-Digital In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Accelerating AI Applications using Analog In-Memory Computing: Challenges and Opportunities.

[BibT_eX]

[DOI]

Shravya Channamadhavuni

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Towards Resilient Deployment of In-Memory Neural Networks with High Throughput.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

An Extension of Fano's Inequality for Characterizing Model Susceptibility to Membership Inference Attacks.

[BibT_eX]

[DOI]

CoRR, 2020

Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current.

[BibT_eX]

[DOI]

Juan Ariel Cabrera

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

DP-MAP: Towards Resistive Dot-Product Engines with Improved Precision.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays.

[BibT_eX]

[DOI]

Steven Lawrence Fernandes

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Detecting Deepfake Videos using Attribution-Based Confidence Metric.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Scalable Construction of Clock Trees With Useful Skew and High Timing Quality.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories.

[BibT_eX]

[DOI]

Vamsee Reddy Kommareddy

IEEE Comput. Archit. Lett., 2019

STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Handling stuck-at-faults in memristor crossbar arrays using matrix transformations.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew.

[BibT_eX]

[DOI]

Wen-Hao Liu

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Software and Hardware Techniques for Reducing the Impact of Quantization Errors in Memristor Crossbar Arrays.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

OCV guided clock tree topology reconstruction.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Clustering of flip-flops for useful-skew clock tree synthesis.

[BibT_eX]

[DOI]

Chuan Yean Tan

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Fast clock scheduling and an application to clock tree synthesis.

[BibT_eX]

[DOI]

Integr., 2017

Clock Tree Construction based on Arrival Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

A Clock Tree Optimization Framework with Predictable Timing Quality.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Delay-driven layer assignment for advanced technology nodes.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Construction of Latency-Bounded Clock Trees.

[BibT_eX]

[DOI]

Chuan Yean Tan

Proceedings of the 2016 on International Symposium on Physical Design, 2016

MCMM clock tree optimization based on slack redistribution using a reduced slack graph.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Cost-Effective Robustness in Clock Networks Using Near-Tree Structures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Useful Skew Tree Framework for Inserting Large Safety Margins.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Construction of reconfigurable clock trees for MCMM designs.

[BibT_eX]

[DOI]

Shankarshana Janarthanan

Proceedings of the 52nd Annual Design Automation Conference, 2015

Fast clock skew scheduling based on sparse-graph algorithms.

[BibT_eX]

[DOI]

Shankarshana Janarthanan

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A study on the use of parallel wiring techniques for sub-20nm designs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Local merges for effective redundancy in clock networks.

[BibT_eX]

[DOI]