Haochen Du
According to our database1,
Haochen Du
authored at least 7 papers
between 2018 and 2025.
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Bibliography
2025
GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024
SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024
RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2018
Proceedings of the 17th IEEE International Conference on Cognitive Informatics & Cognitive Computing, 2018