Haochen Du

According to our database1, Haochen Du authored at least 12 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
GATPE: A High-Performance Edge-Device GAT Processor with Multi-Layer Data-Variation Mechanism.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

GTPE: A 28nm 33.12 TFLOPS/W GNN Training Processor with Unstructured Multi Threshold Pruning, Hybrid Multi-mode Approximate Computing and QUIRE Number System Support.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

MPE: A Power-Efficient Edge-Device Mamba Processor with Multi-Dimensional Calculation-Compression Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

UPE: A Device-Edge DNN Inference Artificial Intelligence Processor with Supporting Reconfigurable Training.
Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

RSPE: A High Energy Efficient SNN Inference Processor with RISC-V based Dynamic Pruning Mechanism.
Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

2024
GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2018
Support Recovery for MWC Based on Random Reduction and Null Space.
Proceedings of the 17th IEEE International Conference on Cognitive Informatics & Cognitive Computing, 2018


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